FMCS Digital Outputs
Figure 7
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737-300/400/500MAINTENANCE MANUAL
E. Processing Units
(1)
There are three independent computing units within the FMC. These are the navigation processor, the performance processor, and the input/output processor. Each computing unit uses identical parallel address/data buses. These buses are independent electrically and physically. The only communication between computing elements is via a mailbox Random Access Memory (RAM) and interprocessor interrupts.
(2)
Navigation Processor
(a)
The navigation processor performs most of the functions associated with navigation computations. These functions are management of the CDU, and lateral and vertical steering guidance. The navigation processor uses a Central Processing Unit (CPU), which executes instructions through the use of a microprogrammed control unit. Integrated circuits are featured in both the control section and the arithmetic section.
(b)
The CPU design allows for efficient execution of floating point arithmetic. This is done through the use of microprogramming techniques and logic circuitry. The entire microprogram is stored in a semiconductor Read-Only Memory (ROM). The logic section uses integrated circuits and a multiplier element for floating point arithmetic.
(3)
Performance Processor
(a) The performance processor performs most of the functions associated with performance computations. These functions are vertical steering guidance (relating to target speeds) and flight envelope protection. It also has a Central Processing Unit (CPU), which is physically identical to the CPU in the navigation processor.
(4)
Input/Output Processor
(a) The Input/Output (I/O) processor performs functions associated with I/O handling. The I/O processor is implemented by a microprocessor. The microprocessor functions in a manner equivalent to the CPUs in the navigation and performance processors. However, the microprocessor does not employ floating point arithmetic.
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737-300/400/500MAINTENANCE MANUAL
(b) The digital interface circuits provided in the FMC are of the type characterized by ARINC 429 Digital Information Transfer System (DITS). The ARINC Input/Output (I/O) circuits provide up to 6 high-speed and 26 low-speed input receivers. The ARINC I/O circuits also provide 6 high-speed and 4 low-speed output transmitters. These ARINC interface circuits are managed by a dedicated ARINC controller. The controller is in turn controlled by an I/O processor. The controller processes all input words on all channels, and passes on to the I/O processor only the required parameters. All other word labels are ignored. This provides for fast response to changes in inputs directly affecting the FMCS's computations. The controller also activates and maintains all output channels.
F. Memory
(1)
The FMC storage is made up of three types of memory: Erasable Programmable Read-Only Memory (EPROM), Nonvolatile Random Access Memory (NV RAM), and High-Speed volatile Random Access Memory (HS RAM). The EPROM contains both program instruction and fixed data, while the RAMs contain the navigation data base and are also used for scratch pad.
(2)
Power for the NV RAM memory is provided by the computer power supply whenever power is applied to the FMC. When power is removed, the memory elements are switched to a low-power standby state for data retention. Power for the standby mode is provided by an internal solid-state dry lithium battery. The battery provides nonvolatile data storage with the RAM memory.
G. Navigation Data Base
(1)
The FMCS navigation data base is stored in the NV RAM memory of the FMC, in two parts. One part contains active permanent data, which is effective until a specified expiration date; the other part contains a set of data revisions for the next period of effectivity. These effectivity dates can be displayed on the CDU. The set of data for the current period of effectivity is selected as the active navigation data base, in order to enable the navigation and guidance functions.
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