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時間:2011-03-26 00:27來源:藍天飛行翻譯 作者:admin
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 2 DP section (Intel 80486)
_ The DP section is used to process the BIT data from the DSP section, to provide information to the front panel display and to provide the data and control signals to the I/O section. The microprocessor in the DP section controls all major functions of the ADF. Programmable Logic Devices serve as the microprocessor controller and provide the interfaces to the memory devices, the data recorder/data loader flash card, and the front panel display driver. The DP receives the ADF bearing reports from the DSP every 50 ms. The DP sends the ADF receiver frequency band select, operational mode select and receiver synthesizer tuning code to the DSP upon the receipt of an external frequency change
R 1EFF : 001-049, 101-105, 151-199, 1 34-53-00Page 25 1 1 May 01/05 1 1 1CES 1 command. The DP performs the QEC and TOP/BOTTOM compensation on the bearing data received from the DSP prior to outputing the bearing data to external systems. Data is exchanged with the DSP section through a dual-port RAM.


 3 I/O section
_ The I/O section provides the interfaces with other aircraft systems including the centralized Fault Display Interface Unit (CFDIU), Control Panel(s), displays and the AFCS. ARINC 429 inputs from the data loader, CFDIU and the tuning control panel(s) are processed by the ARINC 429 Large Scale Integrated (LSI). This LSI also provides the ARINS 429 data loader, CFDIU and deviation outputs. External buffers are used to satisfy the ARINC 429 characteristics for the transmitters. All discrete inputs external to the ADF Receiver are processed by the I/O section. This section also generates the external discrete outputs. The I/O section also contains an RS-232C test interface.
 (c)
 Power Supply Module The 115 VAC, 400 Hz aircraft power is converted by the Power Supply into the DC operating voltages required by the various modules within the ADF receiver. A self-contained, high efficiency switching power supply is used to minimize power dissipation. Five voltages (+5, +12, -12, +20 and +24V) are supplied and a Power Down Interrupt that provides avanced notice of a power loss allowing the processors to temporarily retain their status. A switching circuitry is provided for the power supply to switch its operating frequency in order to prevent a degradation of the receiver sensitivity.

 (d)
 HIRF/Rear Interconnect Module The signal and power cables are on the rear interconnect located inside this High Intensity Radiated Field (HIRF) compartment. The filtered lines are then fed to the appropriate points in the unit. The filtering is accomplished using discrete and distributed shunt capacitance for HIRF filtering. The series resistance, required to limit lightning-induced currents, also forms a series element to HIRF filtering.

 (e)
 Front Panel Display The front panel contains a low-power Liquid Crystal Display (LCD) used as a fault display and as an operator interface during certain modes and display drivers. The front panel display also provides user interfaces for test and troubleshooting.


R 1EFF : 001-049, 101-105, 151-199, 1 34-53-00Page 26 1 1 May 01/05 1 1 1CES 1


 (f) Memory Card Interface Module The ADF receiver is provided with an interface for a Personal Computing Memory Card Interface Adapter (PCMCIA) "flash card" which gives the capability to record data or be configured for read only memory (means to load new software without opening the unit to replace Programmable Read Only Memory (PROM), maintenance and problem installations).
 (4) Not Applicable

R **ON A/C 051-051, 053-099, 106-149, 201-299, 301-399, 401-499,
 (3) Internal description The receiver determines the relative bearing to any selected transmitter operating between 190 and 1799 KHz. This bearing data is converted into ARINC 429 format and transmitted through ARINC buses to the NDs via the DMCs. In addition the AM modulation of the carrier wave is detected and applied to the audio integrating system. The receiver is housed in an ARINC 2MCU case and consists of the following interconnected assemblies:
 (a)
 An ARINC interconnect assembly which provides filtering against HIRF and noise entry or exit.

 (b)
 A digital instrumentation assembly which contains the system processor and signal processor:


 1 The function of the system processor is to:
_
 -format the ADF data from the signal processor into an ARINC 429 bearing word
 -provide frequency tuning for the ADF receiver
 -perform functional test and self-test functions
 -provide diagnostic data to the maintenance processor
 -transmit data generated by the system processor and maintenance processor
 -store calibration constants (as received from the signal processor) in the system processor Non-Volatile Memory during the calibration mode
 -
 
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