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 (s) CPU Failure Protection
 1)  A CPU failure exists if one of the following conditions are true: a) The CPU power supply has failed. b) Watchdog timeout. c) Three software errors occur in the software within 1
 second. d) The CPU power supply overvoltage. e) Watchdog circuit has failed during power-up reset test.
 2)  If a CPU failure occurs, the BCU will perform the following: a) Command the adjacent AGCU to trip its APB. b) Trip the adjacent GHR, GSSR, GSTR, and XPC. c) Load management relays assume their normally closed
 position. d) ARINC 429 transmitter will be turned off. e) The frequency reference signal will be turned off. f) The RDNT DP is enabled. g) Autoland isolation confirmation signal remains
 grounded. h) APU speed-jogging signals are turned off. i) BCU ALIVE signal remains high.
 (t) BCU Power Supply Failure Protection
 1)  If a BCU power supply failure occurs, the BCU will perform the following: a) Load management relays assume their normally closed
 position.
 b) ARINC 429 transmitter is turned off.

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 c) Frequency reference signal is turned off.
 d) Autoland function is disabled.
 e) BCU alive signal goes off.
 f) RDNT DP is not operative.
 g) Trips the GHR, GSTR, GSSR, adjacent APB, XPC, and SSB.
 h) Signals the opposite BCU to trip the SSB through use of

 the BCU alive signal. i) Signals the adjacent GCUs to trip their associated BTBs
 through use of the BCU alive signal.All system faults and protective trips which occur are in the nonvolatile memory (NVM) of the GCU or BCU that sensed a fault and caused a trip. The BCUs act as collectors and classifiers for the received data and transmit processed information over the data bus to the airplane EFIS/EICAS interface unit (EIU). The EIU formats the received data for use by the EICAS and central maintenance computer system (CMCS).A BCU interfaces with the opposite BCU, four GCUs, and adjacent AGCU for BIT informations. BIT functions performed by the BCU include BIT, ground self-test (GST), and power-up/replacement test (PURT). 1) When the BCU is powered and not in a test mode, BIT
 operation will take place and perform protective trip isolation and BIT monitor.
 2)  Protective trip isolation BIT begins automatically after an XPC, APB, GHR, GSSR, or GSTR protective trip. When a protective trip occurs, the protection function which caused the trip is isolated and stored in NVM. Bit monitor continuously searches the EPGS for active and passive faults which do not cause a protective trip. Monitor BIT checks various circuits to be sure of operation within a certain range. If a passive failure is detected, monitor BIT identifies the cause of the failure and stores a corresponding message in NVM. At the same time, the BCU continuously sends the corresponding message to the EIU. If the passive failure goes away, the BCU stops sending the message to the EIU.
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 3)  When the airplane is on the ground, the GST is started after the BCU receives a request from the opposite BCU or CMCS. The BCU performs tests on all its internal components and circuitry, including NVM. Any faults detected during the test are classified and isolated. The shop relevant fault (SRF) messages are stored in NVM and the line relevant fault (LRF) messages are transmitted to the EIU. The BCU also requests each GCU and the opposite BCU to perform its tests upon request from the CMCS.
 4)  The power-up/replacement test is performed automatically when power is applied to the BCU and the airplane is on the ground. The tests performed are identical to that of the GST, except NVM is not tested.
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