(b)  
The power supply module consists of a power supply control card and a power supply card. The power supply converts the ac input to six dc voltages. It provides a separate unswitched (keep-alive-power) for the on/off logic circuitry. It has enough storage capacity to maintain its power output and normal activity during brief power interruptions of less than 200 milliseconds.

 (c)  
The ARINC I/O (input/output) card receives data on six low-speed ARINC 429 buses (3 FCC, 2 FMC, 1 TMC). The card provides the buffering, level changing, and temporary storage of the input data. It transmits data on one high-speed and three low-speed ARINC buses. The high-speed bus transmits data to the EICAS display. The low-speed buses transmit data to the three flight control computers and the thrust management computer. The ARINC I/O card provides the timing and drive capability for the ARINC input and output buses.

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(d)

(e)

(f)

(g)

(h)

(i)

(j)

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MAINTENANCE MANUAL

The I/O functions card provides the digital line buffers, latches, drivers, and decoders which interface discrete inputs and outputs to the microprocessor central bus. The card accepts 16 strapping inputs including four spares, two air/ground discretes, and seven panel switch inputs. It also has eight functional test outputs and three annunciator outputs.Program memory is supplied by two cards that provide up to 56K bytes of Ultra Violet Erasable PROM (UV EPROM). The EPROM contains the programming that is controlled by the executive routine in the central processing unit (CPU). The programming manages the power-up initialization, power interrupt management, mode switching, periodic functions management, and power-down routines. The mode switching routine controls the auto-on, power-up, self-test, flight faults, and ground test routines. During the power-up self-test, the MCDP does not accept flight fault data. It only accepts or displays flight faults after the a successful self-test.The processor card contains the CPU, scratch pad memory, and Electrically Alterable ROM (EAROM). The CPU's internal executive routine controls the programming in the program memory cards.The scratch pad memory is used for temporary data storage during program execution.The EAROM is used for non-volatile storage of flight faults. It can store up to ten flights with faults with each computer sending a maximum of five faults per flight.The display module consists of a display control card and a 32 character alpha-numeric gas discharge display. The display control stores the display data received from the CPU in its internal 96 x 8 bit RAM. The display control also contains the seven front panel switches and three annunciators that allow maintenance personnel to interface with the MCDP.There are two interconnect boards, rear and sideboard. The rear interconnect board routes incoming and outgoing signals between the ARINC 600 connector and the internal elements of the MCDP. The sideboard interconnect board contains the central bus. The central bus transfers the data between the internal elements of the MCDP and the front panel control board or the rear interconnect.
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757
MAINTENANCE MANUAL

 (9)  Option pins allow a standard MCDP design to be customized by selecting applicable programming. The selecting is done by grounding (logic one) or leaving open (logic zero) the appropriate discrete option pins. These pins are located in the main connector on the back of the MCDP and are controlled with airplane wiring. Three pins are used to select the airplane configuration, one pin to select single FMC option, and another pin for dual FCC option. Five pins are reserved for customer options.
 (a)  
Airplane Configuration Pin 1 is set to logic one and pins 2 and 3 are set to logic zero for 757 airplanes.

 (b)  
The single FMC option pin set to logic zero indicates the dual FMC option.
　
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