| | | DATA SOURCE | | -----------| | FCC=1 | | | FMC=2 | | | TMC=3 | | | X X X X X | | -----| | | | | | | | DECIMAL CODE ASSIGNMENT (FIM 22-41-00 | | -------------------------FAULT ISOLATION | | | PROCEDURES) | | | CHANNEL | | ---------| | L=1 | | R=2 | | C=3 | | | | GROUND FAULT DIAGNOSTIC DISPLAY FORMAT * | | | | * NOTE: Ground fault diagnostic display is the same as | | flight fault format except the intermittent bit is | | omitted. | | | 2.................................................................1
(l)
The MCDP remote control panel switches are in parallel with the switches on the MCDP. The MCDP display is duplicated on the EICAS display when the CONFIG/MCDP switch is selected on the EICAS Maintenance Panel (on the P61 panel). Operation and display using the remote control panel and EICAS display is the same as the standard MCDP control and display.
(2) MCDP Power-Up and Self-Test (Fig. 4)
(a) The MCDP power supply requires a 115v | 10 vac, 400 | 30 Hz, single phase power. It receives power from the left ac bus through a circuit breaker on panel P11-3. The MCDP has individual ac, dc, logic, and chassis grounding. The MCDP power supply is isolated from its ac source by a transformer. The ac to dc power conversion is accomplished with full wave, center tapped, rectifier circuits with noise suppression. Filter circuits limit output voltage ripple to approximately 5 percent.
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(b) The dc outputs consist of four switched and three unswitched voltage sources and a separate unswitched 5 vdc Keep-Alive-Power (KAP). The 5 vdc KAP that is on whenever there is power on the airplane. The KAP is center tapped directly off the transformer and is regulated with a zener diode. The KAP enables the ON/OFF control logic, which causes full-power voltage regulators operation. All dc supply levels, except the 5 vdc, are monitored so that an out-of-tolerance voltage causes the FAIL annunciator to turn on. A second 5 vdc supply is a regulated switched supply. An unregulated 25 vdc supplies its regulator. A 25 vdc monitor detects impending power loss and generates an output interrupt signal to the CPU when unregulated voltage drops below 18 vdc. The switched 5 vdc voltage level is monitored so when the level falls below
4.75 vdc a HOLD signal is sent to the CPU. Operation of the CPU is then inhibited.
(c) Automatic Power-Up and Self-Test 1) Automatic power-up and self-test is initiated by an on-ground indication from either air/ground relay. This triggers two pulse circuits in the control logic. One pulse circuit turns on the power supply and instructs the CPU executive module to do the power-up and latch routine. The other pulse circuit starts the three minute timer and generates the AUTO ON signal to the self-test manager module. 2) The executive module (through the power-up and latch routine) checks that the regulated 5 vdc supply has a minimum level of 4.75 vdc. If the voltage is within limits the power latched-on flip-flop is set, and provides a POWER LATCHED ON signal to the self-test module. 3) The CPU reads the option pins to determine airplane configuration (757 or 767), number of FMCs and FCCs, customer options, and parity. The option pin data is stored for use in program routines.
4) The POWER LATCHED ON signal to the CPU enables the self-test routines. The AUTO ON signal selects which self-test routines are performed. When the AUTO ON SIGNAL is enabled, only the scratch pad memory check and program memory check are performed. The other five self-tests require operator interaction or cannot be accomplished when the airplane is in the air or rolling down the runway. A self-test failure causes the CPU to send a reset signal to the power latching flip-flop. The reset flip-flop signal removes the power regulators control signal. This switches the regulators off and removes operating power. A successful self-test allows the three minute timer to expire. This removes the AUTO ON signal and triggers a pulse circuit that sends a reset signal to the flip-flop after three minutes.
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