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 -DSP section,
 -CPU section,
 -I/O section.
 1 DSP section
_ The DSP section processes the analog outputs from the RF module and generates automatic gain control and test signals to the RF module. The localizer and glide slope signals from the RF module are digitized using an A/D converter. The A/D converter is also used to monitor signals from the BITE test points on the RF module and the power supply voltages. The digitized data from the A/D converter is stored in a FIFO which is accessed by the DSP. Within the main DSP, the raw data is formatted and sent to the monitor processor via a serial port prior to the primary processing. The main DSP also sends a time mark to the monitor processor to synchronize the processing of the data sets. 90 Hz and 150 Hz tones are recovered from the digitized localizer and glide slope signals and the deviations are computed based on the depth of modulation of the 90 Hz and 150 Hz tones. Programmable Logic Devices (PLDs) are used by the DSP to generate the control signals for the localizer and glide slope frequency synthesizers. A D/A converter generates the AGC and test control signals for the RF module. A second D/A converter generates the audio outputs. Data is exchanged with the CPU section through a dual-port RAM, providing maximum throughput of both processors.
 2 CPU section
_ The CPU section processes the data from the DSP section, to provide information to the front panel display and to provide the data and control signals to the I/O section. The data processor (Intel 80486SX) in the CPU section controls all major functions of the ILS receiver. PLDs serve as the microprocessor controller and provide the interfaces to the memory devices (boot routine, program, fault and data), the data recorder/data loader, and the front panel display driver. The data processor also does an independent comparison of the main and monitor DSP deviation computations.
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 Data is exchanged with the DSP section through a dual-port RAM. Data is also exchanged with the monitor processor board through a second dual-port RAM. Each processor has a watchdog monitor that monitors expected processor periodic operation. In the absence of such operation, a failure warning is issued.
 3 I/O section
_ The I/O section consists of ARINC 429 drivers and receivers, discrete I/O logic and an RS-232C test interface. The I/O section provides the interface with other aircraft systems including the Centralized Fault Display Interface Unit (CFDIU), data loader, control panel(s), displays and the Automatic Flight Control System (AFCS). ARINC 429 inputs are processed by a specially designed ARINC 429 Large Scale Integrating (LSI). This LSI also provides the ARINC 429 deviation signals. External buffers are used to satisfy the ARINC 429 characteristics for the transmitters.
 (c)
 Monitor processor board The Monitor processor board provides a redundant dissimilar signal processing path for the localizer and glide slope signals from the main DSP. In order to determine if the main CPU section operates properly, the monitor processor calculates the deviation outputs and compares the results against those being transmitted over the ARINC 429 ILS output ports. If the calculations from the two microprocessors are excessively different, the monitor processor asks the DP processor in the main CPU section to set the deviation words to indicate FAILURE. The monitor processor shuts down the output buses if the SSM of the output words does not indicate failure when required.

 (d)
 Power supply Assembly The 115VAC, 400Hz aircraft power is converted by the power supply into the DC operating voltages required by the various modules within the ILS receiver. A self-contained, high efficiency switching power supply is used to minimize power dissipation. Four voltages (+5, +12, -12 and +28V) are supplied and a power-down interrupt provides advanced notice of a power loss, allowing the processors to temporarily retain their status. The power supply provides a transparency time of at least 200 ms to the ILS.

 (e)
 Rear interconnect module To prevent High Intensity Radiated Fields (HIRF) from entering via rear connector cables, a HIRF compartment is formed in the rear of the ILS. The signal and power cables are filtered by

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 using discrete and distributed filter elements and limiting devices on the rear interconnect module located inside this HIRF compartment.
 (f)
 Front panel display module The front panel display contains a low power Liquid Crystal Display (LCD) and display drivers. The LCD is used as a fault display and as an operator interface during certain modes. The display is driven by the CPU section of the main processor module. The front panel display also provides user interfaces for test and troubleshooting, including the push-to-test pushbutton switch and the 9-pin D connector.
　
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