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時(shí)間:2011-03-26 00:13來源:藍(lán)天飛行翻譯 作者:admin
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 On the monitor processor side, Localizer and Glide labels are sampled from output buses 1 and 2 and then compared by the monitor to its own (saved) computed deviations based on the same criteria. The monitor processor and the DP treat the failures specific to the localizer deviation independent of the failures specific to the glide slope deviation. Failure persistence counters are implemented such that intermittent erroneous outputs with a rate of 4 Hz or higher are detected and flagged (i.e. the SSM set to FW) within 500 ms. Each failure persistent counter is implemented such that any combination of errors leading to at least seven miscomparisons out of 10 consecutive samples are flagged as failures within 500 ms. Alternating errors (one good and one bad) are flagged as failures within 1 s.
 1EFF : 001-004, 1 34-36-00Page 31 1 1 Config-1 May 01/05R 1 1 1CES 1


 4
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 5
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 6
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ARINC 429 bus shutdown
 The monitor processor attempts to shut down buses 1 and 2
 after sending a deviation comparison failure indication to the
 DP for a period of 500 ms, when the SSM of the failing
 deviation output still indicates "Normal" and the failure
 condition is still present. If the unit is in the interrupted
 mode of operation, the buses are shutdown. Once the output
 buses are shutdown, the monitor restores both output buses for
 two output cycles (less than 150 ms but greater than 100 ms)
 every two seconds to monitor their outputs.
 The monitor does not restore the activity on the bus until the
 integrity of the unit is reacquired. The ability of the
 monitor processor to shutdown the bus is verified upon power
 up.

BIT (Built-In Test)
 In addition to the redundant path computations and deviations
 cross-comparison, a number of hardware components and software
 processes are monitored by the BIT manager program resident in
 the Data Processor (DP). The main DSP collects data from
 sensors in the RF module. This status data along with power
 supply data, output status data, program activity status data,
 and status data collected from the monitor processor (MON) are
 fed to the BIT manager. The BIT manager filters the data and
 initiates failure warnings when limits are exceeded.
 The BIT manager is initiated eight times a second. High-rate
 faults are monitored eight times a second. Low-rate faults are
 monitored once a second. Upon activation, faults are reviewed
 if they have alarmed. Alarms are controlled by the fault
 invocation rate which is set to either 125 (High-rate) or 1000
 (Low-rate) ms. Failures are transmitted on the ARINC 429 buses
 at an average exposure time of 3 seconds. Failures that have
 an impact on the integrity of the output are reported faster,
 nominally within 500 ms, on either or both labels 173 and 174
 depending on the nature of the failure.

ARINC 429 input
 The selected input ARINC bus is monitored for valid labels,
 SDI, word rate and odd parity:

 -words with invalid label or SDI are ignored,
 -concerning frequency data, if the word rate drops below 3 words per second, or if the data do not contain a valid ILS frequency (which means SSM to Normal Operation (NO) and existing ILS channel), the output frequency word is set to NCD. In fact, unless two consecutive valid input frequency words are received, the ILS holds its last valid frequency, and sends it out at 5 words per second with an NCD coded
 1EFF : 001-004, 1 34-36-00Page 32 1 1 Config-1 May 01/05R 1 1 1CES 1


 SSM. As described above, the SSM of the input frequency word is monitored for NCD condition. In this particular case, the SSMs of the transmitted deviation output words are forced to NCD. In all cases, if tune/test inhibit is asserted, frequency data on the ARINC input is ignored.
 (b) Test mode monitoring
 -the self-test modes provide a check of all deviation-affecting circuitry: as described in Para. (2) internally generated RF carriers with known deviation levels are applied to the receiver inputs. The ILS must then supply an output word with the expected value of deviation. In this way, a satisfactory self-test provides confidence that the ILS is providing correct deviation from modulated RF signals.
 -additionally, during power-up self test, the ability of the monitor DSP to shut down the buses is tested.
 -faults detected during test mode set the SSM of the appropriate deviation word according to the test result. Once the fault is cleared and another test is performed and passed, then normal operation is resumed.
 
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