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forwarded) until the bandwidth again is within its specified limits. This ensures that
correctly working ESs not violating the switch configuration are guaranteed their
allocated bandwidth.
In a properly configured and working AFDX network, a violation of the switch
configuration will never occur. However, if an ES for one reason or another starts to
malfunction, it could cause the switch to get flooded with data which it will then
handle according to its bandwidth limitation policing.
As an example, a malfunction of an ES could cause it to send an erroneous data
stream on network A, while an identical but faultless data stream is also sent on
network B. Since all ESs eavesdropping on this data receive both the erroneous as
well as the valid data stream, one of the two has to be eliminated in any case. Due to
the inherent data integrity checking of all eavesdroppers, the erroneous data stream is
automatically eliminated and only the valid data stream is passed on to the upper
layers. In this example the network A data is eliminated while the network B data is
forwarded and further processed.
According to the standard, an AFDX switch must be equipped with at least 20 ports,
i.e. it must be able to interconnect at least 20 ESs.
Figure 1:
AFDX network
architecture
AFDX Network Architecture
12/30 􀁟 700008_TUT-AFDX-EN_1000
Physical Topology
Figure 2: Physical topology of AFDX
As depicted in Figure 2, each channel of an ES is connected to a switch port via a
cable containing two twisted pair wires interconnecting the input and output ports of
the ES and switch.
Since AFDX is based on the Ethernet standard IEEE 802.3, it uses standard Ethernet
(MAC) controllers for the communication.
For reasons of simplicity Figure 2 only depicts one of the two networks, i.e. the
interconnections between one of the ES's channels and the switch. The second
network has an analogue interconnection; however, it uses the ES's second channel
and a second switch.
Logical Topology
AFDX® / ARINC 664 Tutorial 􀁠 13/30
Logical Topology
Figure 3 shows an example of the logical topology of two ESs communicating with
each other. ES 1 transmits the messages 1, 2 and 3 to ES 2 using a common virtual
link (VL) which is encoded in the destination MAC address. An AFDX message is
uniquely identified by its UDP source and destination port numbers, its IP source and
destination addresses as well as its MAC destination address which encodes the VL.
In the example, the three messages are uniquely identified as follows:
􀂄 Msg 1: UDP Port x Src + IP Src + VL + IP Dst + UDP Port a Dst
􀂄 Msg 2: UDP Port y Src + IP Src + VL + IP Dst + UDP Port b Dst
􀂄 Msg 1: UDP Port z Src + IP Src + VL + IP Dst + UDP Port c Dst
Figure 3:
Logical
topology of
AFDX
UDP Port
x Src
Msg 1
UDP Port
y Src
UDP Port
z Src
IP Src
Msg 2 Msg 3
UDP Port
a Dst
IP Dst
UDP Port
c Dst
UDP Port
b Dst
Msg 1 Msg 2 Msg 3
Switch
VL

AFDX® / ARINC 664 Tutorial 􀁠 15/30
AFDX Communication Concept
The Virtual Link (VL)
Each network of an AFDX ES is connected to the switch via a single cable. This
means that the communication between two AFDX ESs takes place over a single
physical communication link. However, from a system or application point of view, it
is possible to establish many logical communication links, called Virtual Links (VL),
which behave like physical links (hence the name Virtual Link) although they all
make use of one and the same physical link. Thus, VLs make it possible to establish a
sophisticated network communication while ensuring a deterministic behavior
through VL bandwidth policing carried out by the switch.
AFDX implements transmit VLs as well as receive VLs. Each transmit VL can only
be assigned to one (1) ES, and an ES is only allowed to transmit on assigned VLs.
The same receive VLs, however, can be assigned to several ESs meaning that these
can be eavesdropping on the same data.
Virtual Link Scheduling
The AFDX traffic shaping is managed by the ES's VL scheduler which multiplexes
the frames of all transmit VLs of an AFDX ES onto the physical link. Each VL is like
a flow of frames and with multiple VLs there are multiple flows of frames that have
to be multiplexed into a single flow of frames. The multiplexing is regulated by the
Bandwidth Allocation Gap (BAG) which is unique to each VL.
The BAG is a timeslot confining the VL's bandwidth by defining the minimum gap
time between two consecutive frames. The BAG value must be in the range 1 - 128
　
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