| SFCC-* |
| SLAT TEST/RESET |
1 ### |<SFCC TEST WTB-RESET>| ### 1R
2 ### |<WTB/POB TEST | ### 2R
3 ### |<SFCC TEST FAILURE | ### 3R
| REPORT (MEMORY READ OUT) |
4 ### | | ### 4R
5 ### | | ### 5R
6 ### | | ### 6R
-----------------------------------------
(4) Set <SFCC TEST. The page that follows is displayed. -----------------------------------
| SFCC-* |
| SLAT SFCC TEST |
|IN PROGRESS |
| |
| |
(a) If the SFCC TEST is satisfactory, the page that follows is
displayed. |----------------------------------| SFCC-* | | SLAT SFCC TEST | |DATE:+++ ++ UTC: ++++ | |NO FAULTS |
If the X computer arm test is not done during the test, this message shows: |OTHER SFCC ARM SIGNAL | |NOT TESTED | | | ------------------------------------ (5) If the SFCC TEST finds the SFCC at fault the SFCC TEST results page
is displayed as follows. -----------------------------------------
| SFCC-* |
| SLAT SFCC TEST |
1L ### |DATE:+++ ++ UTC: (time) | ### 1R
|PERFORMED WITH FAULT |
2L ### |<FAULT DATA | ### 2R
3L ### | | ### 3R
4L ### | | ### 4R
5L ### | | ### 5R
6L ### |<RETURN | ### 6R
-----------------------------------------
(6) Set FAULT DATA. The page that follows is displayed. -----------------------------------------| SFCC-* | | SLAT SFCC TEST | |DATE:+++ ++ UTC: (time) | |FAILURE DATA | |LANE 1 : 0 0 0 0 0 0 | |O/P L 1 : 0 0 0 0 0 0 0 0 0 0 0 0 | |C/S L 2 : 0 0 | |IP : 0 0 0 0 0 0 0 0 0 0 0 0 | |LANE 2 : 0 0 0 0 0 0 | |O/P L 2 : 0 0 0 0 0 0 0 0 0 0 0 0 | |C/S L2 : 0 0 | |ARINC : 0 0 0 0 0 0 0 0 0 0 0 0 | |<RETURN PRINT>| -----------------------------------------
NOTE : LANE 1 is Lane 1 test
____
- O/P L1 is Output test from lane 1
- C/S L1 is Common services and PCU test from lane 1
- I/P is Test of input discretes LANE 2 is Lane 2 test
- O/P L2 is Output test from lane 2
- C/S L2 is Common services and PCU test from lane 2
- ARINC is Arinc test
(7) If the SFCC-TEST is done and the SFCC periphery is not complete, an SFCC-TEST result page is transmitted to the CFDS to indicate the status. SLAT or FLAP is added to the title.
----------------------------
ù SFCC-* ->ù
ù SLAT SFCC TEST ù
1L ###ù DATE: UTC: ù### 1R
ù NO FAULTS BUT ù
2L ###ù* ù### 2R
ù ù
3L ###ù** ù### 3R
ù ù
4L ###ù ù### 4R
ù ù
5L ###ù ù### 5R
ù ù
6L ###ù<RETURN PRINT>ù### 6R ----------------------------SFCC test result page for SFCC periphery not complete, see Para (8).
(8) SFCC test result page for SFCC periphery not complete.
(a) "*" shows in case of X-computer arm test not being done during test, the message that follows is shown on line 5 and 6.
2L ###ùOTHER SFSS ARM SIGNAL ù ùNOT TESTED
(b) "**" shows the peripheral faults or system messages that are not
complete. either ùWTB SET ù and/or ùNO WTB POWER ù and/or ùLH WTB SOLENOID X/X ù and/or ùRH WTB SOLENOID X/X ù and/or ùFPPU FAULT ù and/or ùLH APPU FAULT ù and/or ùRH APPU FAULT ù
NOTE : X/X shows short circuit (S/C) or open circuit (O/C).
____
(c) If more than one page is needed the "->" code is shown in the 24th character of line one of each SFCC test result page.
(d) The results of previous SFCC-TEST (automatic integrity test and maintenance SFCC test) can be shown with "SFCC TEST FAILURE REPORT" selected from the TEST/RESET MENU key "3L". 中國航空網 www.k6050.com 航空翻譯 www.aviation.cn 本文鏈接地址：A320 Trouble Shooting Manual 排故手冊 飛行操縱 2(92)
