(8)  
Path Descent Speed Targets

 (a)  
For path descents, a speed profile is first predicted and stored by waypoint. Each pair of consecutive waypoints forms a segment of the descent speed profile, with a stored speed for each waypoint. When the speed changes in a segment, a gradient is calculated and used to change the target speed linearly as a function of the distance between the waypoints. The most significant application of this gradient, in path descents, is in the level flight deceleration segments at 10,000 feet and at approach altitude.

 (b)  
As the descent profile is actually being flown, the vertical deviation from the reference path is used to adjust the target speed when the airplane is above the path. This adjustment recognizes that excess energy is inherent in the airplane position above the path, and compensates the target speed accordingly. The energy compensated target speed is not allowed to fall below minimum values which are computed as a function of flap position.

 EFFECTIVITYùùùùùùùùùùùùùùùùùùùùùùùùùùùùùù. AIRPLANES WITHOUT EFIS ú

 34-62-00

 ú ú 03 Page 54 ú Feb 25/87
BOEING PROPRIETARY - Copyright (C) - Unpublished Work - See title page for details.
A
737-300/400/500MAINTENANCE MANUAL
 (9)  Vertical Path Updates and Modifications
 (a)  Updates to the predicted path are performed whenever significant events occur in the flight, such as flight plan waypoint changes, speed or altitude restriction changes, early or late descent. Updates are also performed periodically during certain stable state conditions; for example, the current subphase of the executed plan is updated every 15 seconds in early or late descent. The most common periodic update is for the path between airplane present position and the lateral TO waypoint, which is accomplished every 15 seconds.
 12. Failure Detection and Alerts____________________________
 A. General
 (1)  A function of the FMC operational flight program is to provide a Built-In Test (BIT). This BIT continuously checks the operational status of the FMCS (both CDU and FMC). In addition, the BIT continuously checks the operational status of airplane sensor systems, which interface with the FMCS. Through these checks the BIT maintains a capable set of FMCS functions should failure of other systems affect FMCS data, or FMCS inputs and outputs. The self-monitoring functions of the FMCS are in three parts:
 (a)  
On-Line (In-flight) Tests

 (b)  
Power-Up Tests

 (c)  
Ground Maintenance Support

 B. On-Line Tests
 (1)  
The on-line BIT tests operate continuously as a background task of the FMCS operational flight program. These tests are automatic and require no initialization by the operator. They function to detect CDU and FMC failures, plus some external system faults.

 (2)  
Control Display Unit

 (a)  On-line tests for the CDU provide a program memory checksum test that adds all of the program memory, to verify that the sum is equal to an expected value. In addition, the on-line tests ensure that the power supply provides adequate power to operate the CDU display and logic circuits. Also the tests verify that the CRT horizontal and vertical synchronization pulse timing is correct. ARINC digital input/output channels are also tested to ensure data is properly received and transmitted, and that data from the FMC to the CDU occurs at the correct refresh rate.
 EFFECTIVITYùùùùùùùùùùùùùùùùùùùùùùùùùùùùùù. AIRPLANES WITHOUT EFIS ú

 34-62-00
 ú ú 03 Page 55 ú Feb 25/87

BOEING PROPRIETARY - Copyright (C) - Unpublished Work - See title page for details.
A
737-300/400/500MAINTENANCE MANUAL
 (3)  
Flight Management Computer

 (a)  
The on-line tests for the FMC ensure correct synchronization of the navigation processor, the performance processor, and the input/output processor. In addition the on-line tests verify that the processors perform all instructions and execute their program sequence in a reasonable amount of time. Also ARINC digital input/output channels are tested to ensure data is properly received and transmitted.

 (b)  
The contents of the navigation processor memory, the performance processor memory, and the input/output processor memory are checked by a Cyclic Redundancy Check (CRC). The CRC is performed on a memory in blocks of 1024 words every second to verify memory accuracy. Each word in a block of memory is passed into the CRC circuit one at a time. At the completion of the block transfer the CRC circuit will contain a checkword. This checkword is then compared with a checkword for that block, which is stored in memory.
　
中國航空網 www.k6050.com
航空翻譯 www.aviation.cn
本文鏈接地址：737-300 400 500 AMM 飛機維護手冊 導航 NAVIGATION 5(5)