(f)  
ILS digital output from the left receiver is provided to the static inverter/ILS processor to be converted to analog dc outputs to drive G/P and LAT pointer and flag movements on the standby attitude/ILS indicator.

 (g)  
ILS digital output from the left receiver is provided to the ground proximity warning computer to compare actual G/S deviation with calculated admissable G/S deviation.

 B. Functional Description - ILS Receiver (Fig. 3)
 (1)  
The internal power supply accepts 115v ac from the NAV RADIO ILS or MMR circuit breakers and provides the various dc voltages needed for receiver operations.

 (2)  
The LOC signal received at the antenna is modulated with 90-, 150-, and 1020-Hz tones. The 90- and 150-Hz signals contain localizer course information while the 1020-Hz signal has station code identification. The localizer input signal (rf frequency) is applied to the LOC receiver channel.

 (3)  
The 90- and 150-Hz tones are recovered and separated, and a voltage proportional to the modulation level of each tone is generated. The CPU computes the LOC deviation based on the difference between the voltages and outputs this deviation to the interface module.

 (4)  
Filter and limiter circuits pass the 1020-Hz signal which is amplified and coupled through a transformer to the audio select panels. A preset output adjustment in the amplifier controls the audio output level. The audio output level is reduced by 10 db when an NCD fault occurs.

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MAINTENANCE MANUAL

 (5)  
The glide slope signal received at the antenna is also modulated with 90- and 150-Hz tones. These 90- and 150-Hz signals contain glide slope course information. Processing of the glide slope 90-and 150-Hz signals is the same as for the LOC signal. The CPU calculates and outputs the glide slope deviation to the interface module.

 (6)  
Output data is converted from parallel to serial format by the ARINC 429 interface module. The left ILS system sends ILS data over an ARINC 429 bus to the three EIU's, the left FMC, the DMU, the static inverter/processor, and the ground proximity warning computer. The right system sends data to the three EIU's, the right FMC, and the DMU. The center ILS system sends data to the three EIU's and the DMU. In addition, the left, right, and center ILS receivers send data to the left, right, and center FCC's respectively, over a separate dedicated ARINC 429 data bus.

 (7)  
The BITE performs self-test procedures on the receiver as part of the CPU stored program. During normal operations, the CPU monitors static signals such as supply voltage and VCO drive signals. It tests LOC and G/S input data at the receiver input and throughout the processing stages to determine low signal level faults. It checks the input tuning data for integrity. The BITE also monitors the output data for comparison with the calculated data output from the CPU.

 (8)  
Any receiver faults detected while airborne are stored in internal memory. In addition, the receiver will output failure warning codes on the ARINC 429 data busses. For receiver failures, an invalid data code is output. For absent or improper ILS input signals from the antenna and/or tuning data input, an NCD code is output.

 C. Functional Description - VOR/LOC Antenna Switching (Fig. 3)
 (1)  
The left VOR/LOC antenna switch receives 28v dc from the ILS ANT SW L circuit breaker and is controlled by a discrete from the left FCC. The left FCC applies a ground to energize the switch to select the VOR/LOC antenna when the airplane is in the air and the FCC is not in approach mode. The switch is deenergized to select the left LOC antenna inside the nose radome when the FCC is in approach mode. The selected antenna provides rf signals to the left ILS receiver.

 (2)  
The left VOR/LOC antenna switch also provides a discrete to the left FCC and to all three EIU's for determining which antenna is the source of LOC rf signals. When the switch is deenergized, the discrete is a ground.

 (3)  
The operation of the right and center VOR/LOC antenna switches is the same as the left, receiving 28v dc from the ILS ANT SW R and ILS ANT SW C circuit breakers, using the right and center FCC for control and sending output to the right and center ILS receiver, to the right and center FCC, and to all three EIU's.
　
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