The WR/PWS uses the "Space address usage" technology defined by the ARINC specification 708A for transmission of information on data bus lines. This is achieved by two different data bus lines, each associated with a control bus line from an EFIS control section of the FCU. Data BUS 1 transmits always data associated to the range selected on EFIS/CAPT (side 1). Data BUS 2 transmits always data associated to the range selected on EFIS/F/O (side 2). The control and data bits of word label 055 are valid at any moment on both DATA BUSES, even if the range selected on sides 1 and 2 of FCU are different.
 1EFF : ALL 1 34-41-00Page 27 1 1 Config-3 May 01/05R 1 1 1CES 1

 6. Component Description
_____________________

R **ON A/C 001-049, 101-105, 151-199,
 A. Transceiver (Ref. Fig. 006, 007) The weather radar transceiver with PWS is a lightweight airborne unit. The transmitter section consists of a crystal-controlled reference oscillator, driver stage and a power amplifier output stage. Pulse widths are either 1.5 microseconds (used to produce the calculated windshear hazard presentation), 6 microseconds or 18 microseconds. Echoes from both the 6 and 18-microsecond pulses are processed to produce targets between 20 and 40 NM. The 6-microsecond pulses are also used for turbulence detection. The master processor is the host control computer for the weather radar system with PWS. It also produces the timing and control signals that control the operations of the modulator/transmitter and receiver, and the weather, turbulence and windshear digital signal processor circuits. The master processor decodes the ARINC 429 mode information from the control unit and selected range. During the transmit period, the radio frequency front end, through its waveguide element, sends the pulse-modulated X-band radar signal to the radar antenna. During the receive period, the radio frequency front end receives signals through the waveguide element and through a filter to the preamplifier. The received signal is mixed to produce the 212 MHz signal which is sent to the receiver. The receiver operates with digital slow AGC and provides high-gain narrow-band amplification. It converts the 212 MHz first i-f signal to a 5 MHz third i-f signal. The receiver 5MHz i-f signal output is applied to an analog-to-digital (A/D) converter at the input to the digital signal processor (DSP) subsystem. The analog-to-digital converter digitizes the detected video signal from the receiver. Three separate video processors process the digitized video signal to accommodate three radar displays with independent range selection. The video processor averages the digitized video data within each range bin. A range bin is defined as the range interval over which the radar data are derived. This is determined by the division of the selected range into 512 equal increments. The range averaged data are stored and filtered at each transmission by the video processors. The ARINC 453 interface circuits format the outputs of the video processors and send them to the DMCs and the EFIS.
R 1EFF : ALL 1 34-41-00Page 28 1 1 Config-3 May 01/05 1 1 1CES 1

 Weather radar - Architecture
 Figure 006

R 1EFF : 001-049, 101-105, 151-199, 1 34-41-00Page 29 1 1 Config-3 May 01/05 1 1 1CES 1R Weather radar - Architecture R Figure 006A

R 1EFF : 051-099, 1 34-41-00Page 30 1 1 Config-3 May 01/05 1 1 1CES 1

 Weather radar - Architecture
 Figure 006B

R 1EFF : 106-149, 201-299, 301-399, 401-499, 1 34-41-00Page 31 1 1 Config-3 Aug 01/05 1 1 1CES 1

 Weather Radar Transceiver - Component Description
 Figure 007

R 1EFF : 001-049, 101-105, 151-199, 1 34-41-00Page 32 1 1 Config-3 May 01/05 1 1 1CES 1 The antenna stabilization circuit is internal to the weather radar transceiver with PWS and is built around a 16-bit microprocessor. It is controlled by a servo loop. Five angles are provided to the microprocessor to solve the stabilization equation (line of sight):

 -aircraft pitch and roll angles
 -selected antenna tilt angle
 -
antenna elevation angle

 -
antenna azimuth angle. The aircraft pitch and roll angles are transmitted by the Air Data/Inertial Reference Units (ADIRUs) in the form of ARINC 429 messages. Only the antenna azimuth control is an open loop and the microprocessor generates the antenna feedback signal. The antenna reaches plus or minus 90 deg., on either side of the aircraft centerline. The microprocessor generates the control signals of the elevation and azimuth drive motors of the antenna; the corresponding angular positions are recopied by synchros located in the antenna and processed by the microprocessor. The output data of the linear amplifier is processed for comparison of the detected signals with a threshold said of medium turbulence. Furthermore corrections are made with respect to the selected tilt angle and to the ground speed transmitted by the attitude bus. The control and monitoring circuit is used for the control of the transceiver, the monitoring circuit of the video processors and the ARINC 429 interface circuits. In addition, the control circuit determines the operating mode of the weather radar, the system gain, the tilt angle and the range selection for the video processor. During the program loop, selected inputs are checked or compared to determine the operational status of the weather radar system with PWS. The results of these checks or comparisons are used to display fault warning messages on the display units and to the Liquid Crystal Display of the front panel of the transceiver. The display contains a sequence of software controlled pushbutton switches that result in different functions when pressed. Once the TEST pushbutton switch is pressed, the display shows TEST IN PROGRESS. At the end of the test, the display shows RADAR OK, INPUT OK if no faults were detected in either the radar or input connections. The maintenance circuit with processor ensures formatting of signals and the interface with the CFDS. The processor is continuously supplied to answer the interrogations of the CFDS. In addition, it has access to a non volatile fault memory to report all failure conditions. The monitor processor also enables to activate the system complete test from the CFDS. The different flight phases are generated from a flight/ground discrete provided by the Landing Gear Control and Interface Unit (LGCIU). This discrete enables the CFDS flight phases to be consolidated.
　
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