VHF Transceiver - Power Supply - Block Diagram
 Figure 007

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 VHF Transceiver (Transmitter Part) - Block Diagram
 Figure 008

R 1EFF : 001-049, 101-105, 1 23-12-00Page 31 1 1 May 01/05 1 1 1CES 1 This signal is within the 118-136.975 MHz frequency range and is amplified in the Class A buffer and predriver amplifiers. The signal is further amplified to a nominal 25-watt level by the Class AB driver and final amplifiers. Modulation from the audio processing is applied at the predriver whenever the PTT or data key is enabled and the corresponding VOICE or DATA mode is selected. The VSWR detector maintains the output RF at a constant level across the frequency band, independent of antenna load variations.

R **ON A/C 051-099, 106-149, 201-299, 301-399, 401-499,
 (f) Frequency Synthesizer A dual loop digital synthesizer is used. The first loop operates at 50 kHz spacing. This output is divided by a fixed divide by 128 digital divider to produce a variable reference in the 3.6 to 5 mHz band. The output loop VCO operates directly at the required VHF frequency, 118 to 158 mHz. This VCO output is divided by a fixed divide by 32 digital divider to the variable reference frequency range of 3.6 to 5 mHz. This signal is then compared in a phase detector with the variable frequency from the reference loop. Aany phase or frequency error is corrected by the negative feedback of the loop. Two VCOs are used: one to operate at the output range of 118 to 158 mHz and one to operate at the reference range of 472 to 632 mHz. A tuning voltage of approximately 5 to 10 Vdc is used to cover the tuning range of each VCO. A common emitter RF amplifier amplifies the output loop VCO to the +20-dBm level where it is routed via a pin diode switch to either the transmitter or receiver RF assembly. A separate BITE is used during self-test and alignment modes to monitor the transmit signal with the receiver. The BITE synthesizer is a single loop indirect phase-locked loop (PLL) providing mixer injection in 25 kHz frequency steps. A single phase-locked loop (PLL) combining dual modulus prescaler and programmable divider provides the PLL function. The BITE synthesizer is powered off when not in use to eliminate any possibility of spurious outputs feeding through to the output of the main synthesizer. When in the self-test or alignment mode, a command from the system processor connects the self-test synthesizer to the receiver mixer while the main synthesizer remains connected to the transmitter.
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 (g) Audio processing (Ref. Fig. 009) The microphone input-circuit provides excitation and couples voice modulation to the compressor circuits. The compressor circuits level the range of input signal amplitudes to maintain a high level of modulation without overmodulating. The compressed signal is amplified and applied to the modulator located on the transmitter assembly. Data inputs are similarly processed and applied to the modulator. In addition to transmitted audio or data control, final receiver audio amplification and filtering are performed on this circuit board. Service adjustments are provided for data and voice audio output levels in accordance with ARINC requirements.
 **ON A/C 001-049, 101-105,
 (h) Data interface (Ref. Fig. 010) The data interface board receives the 32 bit, BCD coded serial word from the RMP. This serial word is input to the port selector which selects either port A (onside port) or port B (offside port) as specified by the select discrete of the RMP. The selected bipolar signal is converted and passed to the 429 LSI. The 429 LSI performs the function of receiving all 32 bits and latching the tuning word in a buffer. It then interrupts the processor where the received tuning word is checked for proper label, SDI, word status and channel frequency data. If the word is determined to be acceptable, it is used to tune the transceiver.
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 VHF Transceiver - Block Diagram of the Audio Processing
 Figure 009

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 VHF Transceiver - Data Interface - Block Diagram
 Figure 010

R 1EFF : 001-049, 101-105, 1 23-12-00Page 35 1 1 May 01/05 1 1 1CES 1 The 429 LSI is also used to receive centralized fault display system (CFDS) commands and maintenance data via a bit 429 input port. The maintenance data is received continuously in normal mode from the centralized fault display interface unit (CFDIU) and it provides information about the aircraft environment which is recorded in the fault memory when a fault is detected by the transceiver. In menu mode, commands from the CFDS are received on this port and the transceiver outputs 429 words to display a menu on the multipurpose control and display unit (MCDU). In the normal mode, the transceiver sends fault message information to the CFDIU when a fault is continuously detected for two seconds, and the fault along with the aircraft environment information is stored in nonvolatile memory. In addition to frequency and 429 BITE port management, the fault analysis is performed by the microcomputer. The microcomputer interrogates various functions on the other modules within the transceiver. The sampled analog and digital information is processed to determine fault priorities. In BITE DISPLAY mode, in the event of a detected failure, additional help screens are provided on the LCD of the front panel of the VDR to locate the detected failure to a module.
　
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