-
the boost input voltage monitor
-
the boost overvoltage monitor
-
the DC/DC converter input voltage monitor
-
the DC/DC converter output voltage monitor For internal use, an auxiliary voltage is generated by a linear regulator.
FCDC Functional Blocks
Figure 002
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Block Diagram of Power Supply for FCDC
Figure 003
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I/O Supply Arrangement
Figure 004
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(3) Power Dissipation The FCDCs have a typical power dissipation of 20 Watts.
R R 4. Interface_________ (Ref. Fig. 005)
R R R R R R R R R R 5. Component Description_____________________ (Ref. Fig. 002) The FCDC is an assembly of seven basic modules: - housing - ARINC 600 connector - protection board - mother board - CPU/PS board - I/O board - OBRM
A. General
(1) Electronic design The FCDC is housed in a 2MCU casing in accordance with the ARINC standard 600. The connections to the A/C wiring are via an ARINC 600 size 2 connector. The FCDC contains five types of Shop Replaceable Units (SRU). These are : - CPU/PS board - I/O board - OBRM - protection board - mother board The configuration of these modules within the FCDC box is shown in (Ref. Fig. 006) The power dissipation of the FCDC is 10W.
(2) Mechanical design The mechanical design of the FCDC has led to the following results :
(a) ARINC 600 case, size 2MCU, size 2 connector.
(b) The FCDC box contains two printed circuits boards :
1_ one board divided into two modules : the processor module and the power supply module.
2 one board dedicated to the five I/O modules :
_
-
I/O modules 1 and 3 : ELAC 1/SEC 1
-
I/O modules 2 and 4 : ELAC 2/SEC 2/SEC 3
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I/O module 5 : CFDIU/FWCs. These boards are inserted from the front of computer. The connection between the I/O board and CPU board is ensured by three flat cables (16 bits I/O data bus).
(c)
A dog house containing a plug-in program memory module (OBRM : On-Board Reprogrammable Module).
(d)
The back panel assy contains the mother board, the I/O connector, the protection board and the power input connector :
1 The mother board and the I/O connector allow the
_ interconnection between the ARINC connector and the functional board (I/O board) as regards the I/O signals.
2 the protection board and the power input connector allow the
_ interconnection between the ARINC connector and the PS board as regards the power supply.
(e)
The weight of the FCDC is 2.3 kg.
(f)
The thermal design allows the equipment to operate for two hours without any air cooling.
FCDC General Interface
Figure 005
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Configuration of Modules within the FCDC
Figure 006
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B. CPU/PS Board The Block diagram shows the CPU/PS Board. (Ref. Fig. 007)
(1)
CPU The 16-bit microprocessor MC 68000 is used as the CPU for the FCDC.
(2)
Clock generator APP clocks of the FCDC are derived from a single crystal oscillator (10 MHz).
(3)
Timer A timer with a time base of 2.0 ms is implemented to provide a real-time base for the software cycles. A second timer is provided to supervise the handshaking on the bus. If a time out occurs, the bus cycle is aborted and the processor enters a trap routine to handle this exceptional condition. A third type of timer is a watchdog timer. The CFU must reset this counter every 25 ms by accessing a specific address.
(4)
Interrupt system A real-time clock (RTC) with an interval time of 2.0 ms is also derived from the CPU clock. This real time clock interrupts the CPU on level 3. An interrupt occurs on level 1 when the watchdog timer sends a timeout signal. This timeout signal indicates that the watchdog timer has not been reset for 25 ms by the system software. An interrupt on level 7 can be generated for test purposes. Interrupt summary :
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