--------------------------------------------------------------| level | event - source | |-----------|------------------------------------------------|
 |  1  |  time-out  - watchdog  |
 |  2  |  not used  |
 |  3  |  2.0 ms  - RTC  |
 |  4-7  |  not used  |
 | exception  |  exceptions  - H/W- or prog. failure |
 |  reset  |  reset  - power-on, BITE  |

 --------------------------------------------------------------Remarks : 1 ->lowest, 2 ->highest interrupt level

 Block Diagram - Processor Board
 Figure 007
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 (5)
 Memories Four different types of memories are implemented on the CPU/PS board :

 -System Internal EPROM (16 Kbytes)
 -EEPROM (32 Kbytes)
 -RAM (16 Kbytes)
 -OBRM EPROM (256 Kbytes) (with 150 nsec access time) initialization, BITE.

 (6)
 Power loss monitoring Facilities are provided to monitor the duration of a power interrupt. If a power-shutdown occurs and the power returns within 3 seconds, a discrete signal will be set to "0". If not, the signal will be "1". Five additional discrete signals indicate the status of the secondary plus or minus 15V power lines for the I/O sections. A "0" indicates that the corresponding I/0 section is supplied with plus or minus 15V. A discrete signal is also used to monitor the "FCDC FAIL" relay position.

 C. Program Memory Module
 (1)
 Characteristics A plug-in memory module is implemented in the doghouse of the box. This EPROM-type memory has a capacity of 256 Kbytes shared in 224 Kbytes for application software and 32 Kbytes (protected) for ground test software. It is directely connected to the processor module by a 53-pins connector.

 (2)
 Operation To change the program, it is necessary to simply remove the module from the doghouse and insert a reprogammed version. Removal of the program memory module causes the processor to go into a defined halt state. The insertion of the program memory module initiates the restart and self-test procedure. The on-ground test software is used for shop maintenance, the access to this software is protected (to avoid an untimely access during operational mode) by means of a mechanism which leads, in case of activation, to a FCDC FAULT on A/C. (Ref. Fig. 008)

 D. I/O Interfaces The I/O interfaces provide the required input/output protection, conditioning and buffering for ARINC 429, discrete and analog signals. The maximum number of I/O signals can be :
 -15 ARINC 429 input channels (low speed)
 -
5 ARINC 429 input channels (low speed for internal wraparound)

 -
5 ARINC 429 output channels (low speed)

 -40 discrete inputs

 -20 discrete outputs

 -4 analog inputs.
 These signals are subdivided into five independent sections. Four of
 these sections are completely identical and are realized by pairs on two
 boards.
 The remaining fifth section is allocated to a third I/O board.
 There is no direct data flow between two I/O sections. The communication
 is completely under the control of the processor module.

 (1) I/O sections 1 to 4 The I/O sections 1 to 4 are dedicated to the EFCS computers (ELAC and SEC). (Ref. Fig. 009) The block diagram shows the major components of one I/O section. These are :
 -bus interface

 Software Selection - Flow Chart
 Figure 008
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 Block Diagram of I/O (INPUT/OUTPUT) - Section 1 to 4
 Figure 009

 -access support
 -ARINC 429 input/output
 -
discrete inputs

 -
discrete outputs.

 (a)
 Bus interface The interface to the processor module consists of a 16-bit bi-directional driver for data, as well as buffered address and control lines.

 (b)
 Access support circuit The access support circuit decodes address signals, generates control signals and buffers intermediate data.

 (c)
 ARINC 429 inputs/outputs The ARINC 429 section is designed to receive and transmit signals according to the ARINC specification. The design is based on HARRIS HS-3282 and HS-3182 chips. The configuration is illustrated. (Ref. Fig. 010) Each HS-3282 chip contains signal conditioning, buffering and monitoring for two input channels. An additional driver (HS 3182) is needed for an output channel.
　
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