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 (b) Realization of the ENGAGE logic signals below to generate the SEC HEALTHY discrete signal and to control the relay K30.
 -
no failure of the two microprocessors : not MPFAIL and not SPFAIL These signals are confirmed and latched

 -
no failure of : watchdog not WD

 -
no overvoltage ELRES

 -pushbutton switch selected ON. SEC HEALTHY will become bad if one of the two units detects a failure. A reset of the microprocessors is performed when a failure is detected, and the ON/OFF button changesto the OFF state.

 (5)
 Output management This function ensures the generation of the output parameters.

 -
the ARINC outputs (DG01) to the FCDC and to the SEC (DG03) are processed in accordance with (Ref. Fig. 042) The FIFO receives the CPU data bus and retransmits it to the parallel-to-serial conversion circuit. The ARINC words are sent to the ARINC modulator for the ARINC 429 standard adaptation. The CPU 186 board generates DGO1 to the FCDC and the ARINC board generates DG03 to the SEC

 -
the analog outputs (DSO) are processed in accordance with
 (Ref. Fig. 028, 043, 044, 045)
 -Analog Outputs

 

 

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 ENGAGE Logic Figure 041
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 ARINC Output Figure 042
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 Elevator Servovalve Control Figure 043
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 THS Control (Motor 2) Figure 044
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 THS Control (Motor 3) Figure 045
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 _______________________________________________________________________________ | NAME | USE | CHARACTERISTICS | | | | I (mA) | R | |_______|________________|_________________________ |_________________________| | ANO 1 |L ELEV SV CTL | I lower than or = to +10 |500 ohms + or - 35% | | ANO 2 |R ELEV SV CTL | and |500 ohms + or - 35% | | ANO 3 |THS CTL | I lower than or = to -10 |500 ohms + or -1% | |_____________________________________________________________________________| | ANO 4 |R SPLR X SV CTL | I lower than or = to -4 |500 ohms + or - 35% | | ANO 5 |L SPLR X SV CTL | and |500 ohms + or - 35% | | ANO 6 |R SPLR Y SV CTL | I lower than or = to + 12|500 ohms + or - 35% | | ANO 7 |L SPLR Y SV CTL | |500 ohms + or - 35% | |_______|________________|__________________________|_________________________|
 The SERVO DRIVE board drives four spoiler servocontrols.
 The output relays are controlled by the MON channel.
 The elevator servo valve currents are generated by the COM SERVO
 DRIVE board and monitored by the COM and MON ENGAGE logic board.
 The control of the THS motors 2 and 3 is shown in
 (Ref. Fig. 044, 045)
 The discrete outputs (DSO) indicate the status of certain functions
 (Ref. Fig. 046)
 The LATCH circuit memorizes the data bus D15 at the address
 determined by A1 to A4 of address bus.
 The LATCH outputs are adapted to standard discrete outputs by an
 adaptation circuit.
 Discrete outputs : SEC1

 -------------------------------------------------------------------------------NAME ELECTRICAL LEVEL TO SIGNAL STATUS -------------------------------------------------------------------------------THR RVS SELECTED COM GND/OC EIU1 GND=SELECTED THR RVS SELECTED MON GND/OC EIU2 GND=SELECTED L ELEV MONG OK COM GND/OC SEC1 MON GND=OK
 SEC2 COM
 SEC2 MON L ELEV MONG OK MON GND/OC SEC1 COM GND=OK
 SEC2 COM
 SEC2 MON R ELEV MONG OK COM GND/OC SEC1 MON GND=OK
 SEC2 COM
 SEC2 MON R ELEV MONG OK MON GND/OC SEC1 COM GND=OK
 SEC2 COM
 SEC2 MON GND SPLR OUT COM GND/OC ELAC1 COM GND=OUT
 BSCU
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 SEC Discrete Outputs Figure 046
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 -------------------------------------------------------------------------------
NAME ELECTRICAL LEVEL TO SIGNAL STATUS -------------------------------------------------------------------------------GND SPLR OUT MON GND/OC ELAC2 MON GND=OUT
 BSCU RLY SEC FAULT COM +28VDC/OC RLY SEC1 +28VDC=FAULT RLY SEC FAULT MON GND/OC RLY SEC1 GND=FAULT
 Discrete outputs : SEC2
 -------------------------------------------------------------------------------NAME ELECTRICAL LEVEL TO SIGNAL STATUS -------------------------------------------------------------------------------THR RVS SELECTED COM GND/OC EIU1 GND=SELECTED L ELEV MONG OK COM GND/OC SEC2 MON GND=OK
　
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