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Watch dog timer, address decoder and interrupt logic The watch dog timer, which is integrated into a gate array, continuously monitors the trigger-watchdog-flag TRW* from the Control register at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 100 ms (which happens if an error occurs during the normal processing state of the CPU), the watch dog timer generates a watchdog-reset (WDR*) signal. This activates the reset logic (also in a gate array), which resets the CPU. The address decoder decodes the addresses on the LOCAL-ADDRESS-BUS and outputs various control-enable signals for the other functional blocks on the board. For example, the control-enable signal CE EPR, enables a read-out from the EPROM section ; or control-enable signal CE BUS enables the COMMON BUS time out control and so on. The interrupt logic determines the interrupt-priority level (IPL) for the interrupt inputs, which are requesting an interrupt in the CPU operation. The interrupt-request-inputs are received from MFPI and MFPII (Ref. Para. 5.A.(2)(a)6). When an interrupt is granted, the CPU sends out function-code-output (FCO) signals back to the interrupt logic, which activates the interrupt acknowledge signal in order to inform MFPI or MFPII that an interrupt has been granted.
Bus requester and bus couplers When the CPU on any DPU board wants access to the COMMON BUS, it puts in a request through the bus requester, integrated in a gate-array, which processes signals mainly obtained from the CPU. It generates a bus-request (BR*) signal, which is sent to the bus arbiter (located on the DPU1 (PFD) board). When the bus request is granted, the bus arbiter sends a bus-grant (BG IN*) signal back to the bus requester, which enables the bus couplers on the board and also asserts a busy signal (BUSY*) in order to inform the bus arbiter that the COMMON BUS is now being used. There are three types of bus couplers on each board - the LOCAL-DATA- BUS couplers, the LOCAL-ADDRESS-BUS couplers and the LOCAL-CONTROL- BUS couplers. These bus couplers enable data transfer between the local buses on the board and the COMMON BUS. The DPU1 (PFD) board has three additional bus couplers - the MEMORY-DATA-BUS couplers, the MEMORY-ADDRESS-BUS couplers and the MEMORY- CONTROL-BUS couplers. These bus couplers enable data transfer between the memory buses on the board and the COMMON BUS.
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COMMON BUS time out control This logic, which is integrated in a gate array, determines how long its CPU can claim access to the COMMON BUS. The time interval begins with signal CE BUS* going active i.e. when the CPU has gained access to the COMMON BUS, and the timing is monitored by a clock from the clock generator. On completion of the specified time interval, a signal BERR* is activated to stop the CPU.
MFPI MFPI (multi-function peripheral) is a 48-pin integrated module containing the following main functional groups:
 -general purpose I/O port (GPIP)
 -interrupt controller I
 -IT generators 1 and 2
 -serial interface I. The CPU on the board can communicate with any of these functional groups via the CPU bus lines (in MFPI). The GPIP receives interrupt-requests (IRQ*) from external devices as well as from the DSDL control logic (TX/R) and routes these to the interrupt controller I. The source of the interrupt-requests from external devices varies on each DPU board. The interrupt controller I handles the interrupt requests received via the GPIP as well as those generated by certain functional blocks inside MFPI. It uses the daisy-chaining principle and as per the priority rules, sends the signal INT MFPI* to the interrupt logic in order to request an interrupt in the CPU operation on the board. The IT generator 1 is a real time monitor and generates definite cycles, during which the CPU can execute various management tasks. The IT generator 2 is a frame time monitor and also generates definite cycles, during which specific routines can be executed on the DUs. In order to perform these operations, both IT generators transmit an interrupt-request each to the interrupt controller I. The serial interface I is basically a UART (universal asynchronous receiver transmitter). It provides asynchronous serial communication with an external device (e.g. a debugger) during maintenance operations.
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MFPII The basic operation of MFPII is similar to that of MFPI. The GPIP, in this case, receives various signals as well as activates output signals. The number of input and output signals varies on each DPU board. Some of the input signals are routed to the interrupt controller II and can claim an interrupt in the CPU operation on the board. The other input signals are status-signals and inform the CPU of the status of their sources. The operation of the interrupt controller in MFPII is similar to that in MFPI. It sends the signal INT MFPII* to the interrupt logic in order to request an interrupt in the CPU operation on the board. There is a real time counter and a baudrate timer in MFPII. The real time counter operates in the event-counting mode and the baudrate timer generates two baudrate clocks : BDRCK SI I for the serial interface I in MFPI and one for the serial interface II in MFPII. The serial interface in MFPII has the same function as that in MFPI and is used during maintenance operations.
　
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