2
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e Watchdog timer and reset logic
_ The watchdog timer continuously monitors the trigger-watch-dog-flag TRW* from the ARINC control register (in ARINC I/O interface logic) at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 350 ms (which happens if an error occurs during the normal processing state of the CPU), the watchdog timer generates a watchdog-reset (WDR*) signal. This resets the CPU via the RESET logic. When the unit is powered on or when the signal WDR* is activated by the watchdog timer, the reset logic resets the CPU.
f Clock generator
_ The clock generator consists of a quartz oscillator and two frequency dividers. The quartz oscillator generates a 20 MHz clock and the frequency dividers divide this clock to output various derivative clocks, which are required on this board.
Discrete I/O interface logic
Five functional groups are discussed under this heading:
-
discrete input interface
-
discrete output interface
-
discrete wrap around test logic
-DMC invalid relay
-discrete decoder.
a Discrete input interface
_ This interface, made up of the discrete input hybrid modules and the discrete input latches, can handle a total of 20 discrete inputs (type OPEN/GND). Under the control of the CPU, the inputs are routed through the I/O-DATA-BUS, the I/O data bus coupler and the CPU-DATA-BUS to the COMMON RAM (on the DPU1 (PFD) board) for storage until further use. The CPU activates TEST MODE and TEST HI/LO via the MFP on the board in order to test the hybrid modules and the latches in this interface.
b Discrete output interface
_ This interface, made up of the discrete output module and the discrete output latch, can handle 4 discrete outputs. These outputs are fetched from the COMMON RAM, under the control of the CPU, and routed through this interface to external peripherals.
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3
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c_ Discrete wrap around test logic
This logic provides a wrap-around-test facility for the
discrete I/O interface logic. The wrap-around loop is
formed by the discrete output interface, a wrap around
hybrid module and a wrap around latch. During the test, the
CPU transmits four bits through the CPU-DATA-BUS and
through this wrap-around-loop and then executes a
status-check.
d DMC invalid relay
_ This relay is mounted on the I/O interface 3 board only. When the DMC is switched on, it executes a short self-test cycle, during which the bit D01 at the output of the discrete output module is LOW. The DMC invalid relay is thereby energized and signal DMC-INVALID is OPEN : an indication that the DMC is not accessible for operation during this time. After the self-test cycle, bit D01 goes to HIGH and remains HIGH during the normal operation of the DMC. This de-energizes the relay and signal DMC-INVALID is held continuously at LOW. In the case of an abnormal condition in the DMC, bit D01 is again set to LOW, causing the signal DMC-INVALID to become OPEN.
e Discrete decoder
_ The addresses on the CPU-ADDRESS-BUS are decoded by this decoder in order to deliver the enable- and clock-signals for the discrete I/O interface logic.
ARINC I/O interface logic
Four main functional groups are discussed under this heading:
-
ARINC interface modules
-
ARINC decoder
-control and status registers
-ARINC latches.
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a
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b
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c
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d
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ARINC interface modules There are nine ARINC interface modules on each I/O interface board. Each interface module contains two receivers and one transmitter, all three operating independently. The function of the receiver is to receive serial data as per ARINC 429 specification via an input channel, convert it into 16-bit words and transmit these through the I/O-DATA-BUS, I/O data bus coupler and the CPU-DATA-BUS for relabelling purpose. The function of the transmitter is to receive 16-bit words through the CPU-DATA-BUS and I/O-DATA-BUS, convert them to serial bits and transmit these via the ARINC output driver to external devices. Each I/O interface board can thus handle a maximum of 18 inputs (6 high-speed and 12 low-speed) and 9 outputs (only 1 output is, however, used).
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