-
enable the ARINC output driver
-perform a general reset for certain sections of the discrete-, ARINC- and serial- I/O interface logic via signal RES I/O*
-trigger the watchdog timer via signal TRW*.
The status register feeds the status-information of
definite signals from the control register back to the CPU
for validity checks.
ARINC latches These latches inform the CPU about the status of the receiver- and transmitter-sections inside the ARINC interface modules via definite signals.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 31 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 4 Serial interface logic
_ There are two serial interfaces on each I/O interface board :
-RS422 interface
-RS232 interface.
a RS422 interface
_ This interface receives serial-data from an external device
i.e. the , converts this data to 8-bit parallel data and loads it on the CPU-DATA-BUS for eventual storage in the COMMON RAM (on the DPU1 (PFD) in the COMMON RAM (on the DPU1 (PFD) board). It consists of a line receiver and an ACIA (asynchronous communications interface adapter). The line receiver renders the serial-data-input TTL compatible and feeds it to the ACIA, which in turn is responsible for the actual serial-to-parallel conversion.
b RS232 interface
_ This interface is used for maintenance purposes and provides a serial communication with an external device
(e.g. debugger). It consists of a MFP (multi-function
peripheral) and two line drivers. The input line driver
renders the external input-data-voltage TTL- compatible for
the UART in the MFP, whereas the output line driver renders
the TTL serial output voltage from the output line driver
renders the TTL serial output voltage from
The MFP which has more functions than those described
above, is an integrated module consisting of the following
functional groups :
-general purpose I/O port (GPIP)
-interrupt controller
-timers A, B and C, D
-UART.
The CPU on the board can communicate with any of these
functional groups via the CPU-bus-lines (also in the MFP).
The GPIP handles two inputs (from the power supply module)
and two outputs (to the discrete I/O interface logic). The
power supply module uses the GPIP for two purposes :
firstly it informs the CPU on the board about the status of
the signal SPID and secondly, it requests an interrupt in
the CPU operation with signal POWER LOW.
The CPU uses the GPIP for only one purpose : it tests the
discrete input interface (in the discrete I/O interface
logic) with signals TEST MODE and TEST HI/LO.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 32 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 The interrupt controller handles interrupt-requests for an interrupt in the CPU operation received via the GPIP as well as those generated internally in the MFP by the UART. It sets priority-levels for these requests ans sends signal IRQ5* (MFP) to the interrupt logic. When the request is granted by the CPU, it receives the signal IACK5* (MFP). The timers A and B are cascaded and operate as a real time counter, whereas the timers C and D provide the baud-rate clocks for the ACIA in the serial interface logic and the UART in this MFP. The UART (universal asynchronous receiver transmitter) in the MFP, as already explained, provides asynchronous serial communication with an external device (e.g. debugger) via the line drivers during maintenance operations. To accomplish this task, the UART operates in the receiver or in the transmitter mode.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 33 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 5 Bus logic
_ The following functional groups are discussed under this heading :
-
bus request logic
-
bus time out logic
-
bus couplers.
a Bus request logic
_ The bus request logic is integrated into a 20-pin gate array module. The gate array also contains the bus time out logic (discussed in this chapter) and the reset logic (discussed under processor logic). The bus request logic consists internally of a bus requester and a bus master control. When the CPU on any I/O interface board wants access to the COMMON BUS, it activates signal CE BUS* via the address decoder (in the processor logic). The bus requester recognizes this signal CE BUS* and sends the bus-request signal BR* to the bus arbiter (on DPU1 (PFD) board). When the request is granted by this bus arbiter, it asserts a bus-grant input-signal BG IN*. Access to the COMMON BUS by any one of the three I/O interface boards is based on priority rules i.e. I/O interface 1 board has the lowest priority among the three boards. Once the bus-grant has been accepted by a bus requester, it sends signal BUSY* to the bus arbiter to indicate that the bus is now being used by its CPU. Signals CE STATUS* (from the address decoder) and bit D15 (on CPU-DATA-BUS) are activated when the CPU claims access to the COMMON BUS. These two signals ensure that signal BUSY* is held in active state as long as communication with the COMMON RAM or BITE memory (both on DPU1 (PFD) board) continues. When the CPU no longer requires the COMMON BUS, it activates ADDRESS-STROBE signal AS* and signal BUSY* becomes inactive.
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