The general function of all three I/O interface boards is
 identical ; each board operating independently due to its own
 processor logic.
 Each I/O interface board consists of five main logic groups:

 -processor logic

 -discrete I/O interface logic

 -ARINC I/O interface logic

 -serial interface logic

 -bus logic.
 There are two logic bus lines on each board : the CPU-bus-lines
 and the I/O-bus-lines. The CPU-DATA-BUS (16-bit, bidirectional,
 three-state) and the CPU-ADDRESS-BUS (20-bit, unidirectional,
 three-state) provide communication with the CPU in the processor
 logic, whereas the I/O-DATA-BUS (16-bit, bidirectional,
 three-state) provides communication with the discrete and ARINC
 I/O interface logic.

 1_ Processor logic
 The following functional groups are discussed under this
 heading:
 - central processing unit (CPU)
 - local data RAM, program PROM and relabelling EPROM
 - address decoder and DTACK generator
 - interrupt logic
 - watchdog timer and reset logic
 - clock generator. 

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 I/O Interface Board - Block Diagram
 Figure 008

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 a
_
 b
_
Central processing unit (CPU)
 The CPU is a 16-bit microprocessor from the MC68020 family.
 It is always in one of the following three processing
 states:

 -normal processing state, which is associated with intruction execution. In this state, the CPU fetches instructions/operands from its program PROM or the COMMON RAM, processes them and stores the final result back in the COMMON RAM. (The COMMON RAM is located on the DPU1 (PFD) board)
 -execution processing state, which is associated with interrupts, trap instructions and other exceptional conditions. In this case, a vector number, which is fetched from the program PROM, is fed to the CPU via the CPU-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the program PROM. This instruction is executed by the CPU in order to carry out the necessary is executed by the CPU in order to carry out the necessary
 -halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
Local data RAM, program PROM and relabelling EPROM When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 2Kx16-bit local data RAM. The program PROM has a total storage capacity of 8Kx16-bit words. It contains the instructions carried out by the CPU during its normal processing state as well as the exception vectors required during the exception processing state - in short, the complete operational software required by this board is stored in the program PROM. The relebelling EPROM has a total storage capacity of 32Kx16-bit words. The relabelled addresses for the COMMON RAM (for the data received through the ARINC I/O interface logic) as well as the test library (for the self tests) and a monitoring program for this board (for maintenance operations) are stored in the relabelling EPROM. All three memories are addressed by the CPU-ADDRESS-BUS and data transfer takes place through the CPU-DATA-BUS. The address decoder provides the enable-signals and the CPU the read/write signals.
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 c
_
 d
_
Address decoder and DTACK generator
 The addresses generated by the CPU are decoded by the
 address decoder in order to deliver the required
 enable-signals on this board.
 The DTACK generator asserts the signal DTACK* in order to
 inform the CPU that the CPU-DATA-BUS is being used for a
 data transfer.

Interrupt logic
 The interrupt logic has two functions:

 -
initiate an interrupt in the CPU operation on the I/O interface board

 -
initiate an interrupt in the CPU operation on the DPU

 board. The two interrupt requests, which can claim an interrupt in the CPU operation on the I/O interface board are IRQ5* (MFP) and IRQ4* (ACIA) from the RS232 and RS422 interfaces respectively (in the serial interface logic). Their priority-level is encoded by the interrupt logic via three interrupt-priority-level signals IPL0* - IPL2* sent to the CPU. When the CPU acknowledges an interrupt-request, it asserts its function-code-outputs FC0 - FC2 and ADDRESS-STROBE signal AS* accordingly. The interrupt logic then activates either interrupt-acknowledge-signal IACK5* (MFP) or IACK4* (ACIA), which informs the RS232 or RS422 interface that an interrupt has been granted. When data from the FMGC or FWC is received by an I/O interface board, its CPU can initiate an interrupt cycle on the DPU board. In such a case, the CPU on the I/O interface board sends relevant addresses through its CPU-ADDRESS-BUS in order to activate signals CE INT1* or CE INT2* via the address decoder. These signals are transmitted via the interrupt logic as signals IRQ1* (FWC) or IRQ2* (FMGC) to the relevant DPU board to claim an interrupt in its CPU operation.
　
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