b
_
 c
_
 The function of the bus master control in the gate array is to generate enable-signals for the bus couplers once access to the COMMON BUS has been attained, so that an information transfer between the local buses on the I/O interface board and the COMMON BUS can take place. The enable-signal EN ADDA* enables the local data and address bus couplers, whereas enable-signal ENS* enables the local control bus coupler. The bus master control is clocked by XCK68K from the clock generator and the bus-acknowledge signal BACK remains HIGH as long as the information transfer takes place. All output signals from the bus requester and the bus master control are reset when the reset logic, also in the gate array is initiated.
Bus time out logic The bus time out logic is also integrated into the 20-pin gate array module. It determines how long the CPU can claim access to the COMMON BUS. The time interval begins with signals CE BUS* and BACK going active i.e. when the CPU has attained access to the COMMON BUS, whereas the timing is monitored by clock XCK68K from the clock generator. On completion of the specified time interval, signal BERR* is activated in order to stop the CPU. This signal can also be activated when the reset logic, also in gate array, is initiated.
Bus couplers There are three types of bus couplers on each I/O interface board - the local data bus coupler, the local address bus coupler and the local control bus coupler and the local control bus coupler. The local data bus coupler consists of two bi-directional line drivers. They enable data transfer between the CPU-DATA-BUS (D00-D15) on each I/O interface board and the COMMON-DATA-BUS (BD00-BD15). They are enabled by the enable-signal EN ADDA*, which is generated by the bus master control when the I/O interface board has been granted access to the COMMON BUS. The direction of the line drivers is determined by signal R/W* from the CPU. The local address bus coupler consists of two uni-directional line drivers. When enabled by signal EN ADDA* (active LOW), they tranfer addresses, generated by the CPU from its CPU-ADDRESS-BUS (A00-A16) to the COMMON-ADDRESS-BUS (BA01-BA16).
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 35 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 The local control bus coupler enables a bi-directional transfer of control signals between the I/O interface board and the DPU1 (PFD) board (common RAM and BITE memory only) via the COMMON-CONTROL-BUS.

 (c) WXR board The echoes of 800 beams are received by the WRX antenna every half revolution (4 s.). Each beam echo contains 512 separate signals corresponding to the strength of the beam reflection at 512 separate points in the airspace in front of the aircraft. (Ref. Fig. 009) The strength of the reflection at each point is converted into a 3 bit code (1 BIN), which is the color mode for that particular point. This information is transmitted serially via an ARINC input channel to the WXR board, i.e. at any given time, 512 x 3 = 1536 serial bits or 512 BINs, which represent the color information of one beam, are received by the WXR board. In addition to the BIN information, the WXR board also receives four control words of 16 bits each as well as two signals, START SYNC and END SYNC, of approximately 3 bits each. The signal START SYNC heralds the start of the input word and signal END SYNC its end. The four control words are fetched by the DPU2 (ND) board and the BIN information is processed directly on this board. The WXR board can be sub-divided into the following main functional blocks: (Ref. Fig. 010)
 -ARINC 708 interface and manchester decoder
 -
beam shift register and file register

 -
beam buffer

 -main memory - output circuitry.
 1_ ARINC 708 interface and manchester decoder
 Four input channels feed WXR serial input words to the ARINC
 708 interface. All inputs are in manchester bi-phase code ;
 the bit-rate in each word being 1 MHz. Only one channel is
 selected for processing by the signal CHANNEL SEL, activated
 by the DPU2 (ND) board via word register 5. The manchester
 bits in the serial input words are transformed to TTL voltage
 levels by this interface and fed via a MUX to the manchester
 decoder.
 (Ref. Fig. 011) 

R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 36 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1

 Weather Radar Serial Input Word
 Figure 009

R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 37 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1

 INTENTIONALLY BLANK

 1 1

31-63-00Page 38
1 1 Config-1 Feb 01/05 1 1 1CES 1
　
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