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 -execution processing state, which is associated with interrupts, trap instructions, tracing and other exceptional conditions. In this case, a vector number, which is fetched from the system EPROM, is fed to the CPU via the LOCAL-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the system EPROM. The CPU executes this instruction in order to carry out the necessary operation
 -halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
Local RAM and system EPROM When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 32 K x 16 bit local RAM. It is addressed by the LOCAL-ADDRESS-BUS and data transfer takes place via the LOCAL-DATA-BUS. It is enabled by an address decoder and the read/write signals are provided by the CPU via the R/W logic. The local RAM has a special power supply line (+5 V PROT.). This provides continuous power to the local RAM even during a short-power-interrupt condition. This same line provides power to the COMMON RAM (on DPU1 (PFD) board) also. The system EPROM consists of program EPROMs and data EPROMs. The program EPROMs contain instructions required by the CPU to execute the operational program. They also contain a test library and a monitoring program for maintenance purposes, which monitor the system hardware, depending on the information received via the RS 232 serial interface. The data EPROMs contain data required by the CPU while executing the operational program. Those program EPROMs and data EPROMs, which contain the operational software, are located in the OBRM in the dog-house mounted on the front side of the unit. Those program EPROMs and data EPROMs are located on the OBRM which consists of a 128K x 32 bit EPROM bank.
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Watch dog timer, address decoder and interrupt logic The watch dog timer, which is integrated into a gate array, continuously monitors the trigger-watchdog-flag TRW* from the Control register at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 100 ms (which happens if an error occurs during the normal processing state of the CPU), the watch dog timer generates a watchdog-reset (WDR*) signal. This activates the reset logic (also in a gate array), which resets the CPU. The address decoder decodes the addresses on the LOCAL-ADDRESS-BUS and outputs various control-enable signals for the other functional blocks on the board. For example, the control-enable signal CE EPR, enables a read-out from the EPROM section ; or control-enable signal CE BUS enables the COMMON BUS time out control and so on. The interrupt logic determines the interrupt-priority level (IPL) for the interrupt inputs, which are requesting an interrupt in the CPU operation. The interrupt-request-inputs are received from MFPI and MFPII (Ref. Para. 5.A.(2)(a)6). When an interrupt is granted, the CPU sends out function-code-output (FCO) signals back to the interrupt logic, which activates the interrupt acknowledge signal in order to inform MFPI or MFPII that an interrupt has been granted.
Bus requester and bus couplers When the CPU on any DPU board wants access to the COMMON BUS, it puts in a request through the bus requester, integrated in a gate-array, which processes signals mainly obtained from the CPU. It generates a bus-request (BR*) signal, which is sent to the bus arbiter (located on the DPU1 (PFD) board). When the bus request is granted, the bus arbiter sends a bus-grant (BG IN*) signal back to the bus requester, which enables the bus couplers on the board and also asserts a busy signal (BUSY*) in order to inform the bus arbiter that the COMMON BUS is now being used. There are three types of bus couplers on each board - the LOCAL-DATA- BUS couplers, the LOCAL-ADDRESS-BUS couplers and the LOCAL-CONTROL- BUS couplers. These bus couplers enable data transfer between the local buses on the board and the COMMON BUS. The DPU1 (PFD) board has three additional bus couplers - the MEMORY-DATA-BUS couplers, the MEMORY-ADDRESS-BUS couplers and the MEMORY- CONTROL-BUS couplers. These bus couplers enable data transfer between the memory buses on the board and the COMMON BUS.
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COMMON BUS time out control This logic, which is integrated in a gate array, determines how long its CPU can claim access to the COMMON BUS. The time interval begins with signal CE BUS* going active i.e. when the CPU has gained access to the COMMON BUS, and the timing is monitored by a clock from the clock generator. On completion of the specified time interval, a signal BERR* is activated to stop the CPU.
　
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