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MFPI MFPI (multi-function peripheral) is a 48-pin integrated module containing the following main functional groups:
 -general purpose I/O port (GPIP)
 -interrupt controller I
 -IT generators 1 and 2
 -serial interface I. The CPU on the board can communicate with any of these functional groups via the CPU bus lines (in MFPI). The GPIP receives interrupt-requests (IRQ*) from external devices as well as from the DSDL control logic (TX/R) and routes these to the interrupt controller I. The source of the interrupt-requests from external devices varies on each DPU board. The interrupt controller I handles the interrupt requests received via the GPIP as well as those generated by certain functional blocks inside MFPI. It uses the daisy-chaining principle and as per the priority rules, sends the signal INT MFPI* to the interrupt logic in order to request an interrupt in the CPU operation on the board. The IT generator 1 is a real time monitor and generates definite cycles, during which the CPU can execute various management tasks. The IT generator 2 is a frame time monitor and also generates definite cycles, during which specific routines can be executed on the DUs. In order to perform these operations, both IT generators transmit an interrupt-request each to the interrupt controller I. The serial interface I is basically a UART (Universal Asynchronous Receiver Transmitter). It provides asynchronous serial communication with an external device (e.g. a debugger) during maintenance operations.
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MFPII The basic operation of MFPII is similar to that of MFPI. The GPIP, in this case, receives various signals as well as activates output signals. The number of input and output signals varies on each DPU board. Some of the input signals are routed to the interrupt controller II and can claim an interrupt in the CPU operation on the board. The other input signals are status-signals and inform the CPU of the status of their sources. The operation of the interrupt controller in MFPII is similar to that in MFPI. It sends the signal INT MFPII* to the interrupt logic in order to request an interrupt in the CPU operation on the board. There is a real time counter and a baudrate timer in MFPII. The real time counter operates in the event-counting mode and the baudrate timer generates two baudrate clocks : BDRCK SI I for the serial interface I in MFPI and one for the serial interface II in MFPII. The serial interface in MFPII has the same function as that in MFPI and is used during maintenance operations.
DSDL control logic The DSDL (Dedicated Serial Data Link) control logic on a DPU board is responsible for a data transfer between that board and its dedicated DU. It sends data to the stroke generator, located inside the DU, and receives data from the DU to test the data-link as well as the stroke generator inside this DU. After power-on or after changing the DU picture mode, the stroke generator program is loaded from the DPU board in the DU and verified. The results of the selftest routines inside the DU are sent back to the DPU boards. The DSDL control logic consists mainly of the DSDL interface and the DSDL switching circuit. The DSDL interface, which consists of a transmitter-and a receiver-section, enables the bidirectional data transfer between the board and the DU. The DU-specific data processed on the board is parallel-to-series converted by the transmitter-section in the DSDL interface and transmitted to the DU via the DSDL transmitter and the DSDL switching circuit. The test-related data from the DU is series-to-parallel converted by the receiver-section in the DSDL interface and is processed accordingly by the CPU. The enabling of the transmitter-section and the selection of the receiver-section in the DSDL interface is executed by the control register and the select logic respectively. (Ref. Fig. 004)
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 The DSDL switching circuit is different on the three DPU boards. It consists basically of two relay units ; each unit having a double-pole two-way switching capability. During normal operation, the relay-units are not activated. A bidirectional data transfer between this DMC and the DU thus takes place. In the case of a breakdown of this DMC, one relay-unit is activated by the external signal DMC3 TRANSFER, and a bidirectional data transfer between the back-up DMC3 and the relevant DU takes place. In the case of a breakdown of an ECAM DU, the second relay-unit is activated by the external signal ND/ECAM TRANSFER and a bidirectional data transfer between an EFIS DU and the DPU3 (ECAM) board (via DPU2 (ND) board) takes place.
COMMON RAM, BITE memory and bus arbiter The COMMON RAM, the BITE memory and the bus arbiter are located on the DPU1 (PFD) board only. The COMMON RAM and the BITE memory are accessible to the DPU and I/O boards through the COMMON BUS. The COMMON RAM has a storage capacity for 16Kx16-bit words. It is divided into definite sections, where computed data from the DPU and I/O boards is stored intermediately until further use. It is addressed by the MEMORY-ADDRESS-BUS and data transfer takes place through the MEMORY-DATA-BUS. The memory address decoder provides the control-signals for the COMMON RAM. A special power supply line +5 V PROT. from the power supply module provides continuous power to the COMMON RAM even during a short-power-interrupt condition. The BITE memory has a total storage capacity of 2Kx16-bit words. A fault indication from any board during a self-test routine is stored in this memory for analysis during maintenance operations. It is accessed in the same manner as the COMMON RAM.
　
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