1EFF : 106-149, 303-399, 1 31-63-00Page 13 1 1 Config-3 Aug 01/05 1 1 1CES 1 The other functions of the processors on the DPU boards are :

 -process status information fetched from the COMMON RAM
 -react to various interrupts
 -provide the frame time for the stroke picture or for the WXR picture (DPU2 (ND) only) on the respective DU
 -control the digital output link to the DU
 -run test routines
 -generate maintenance information
 -control WRX beam information (DPU2 (ND) only). To achieve all these functions, a powerful software program and data handling is implemented in each DPU. Changes in the software for a DPU can be executed very easily - without the need of removing or dismantling the entire unit. The relevant memory module, which contains the whole software can be effortlessly pulled out of the dog-house on the unit in order to execute the changes. Data communication between the I/O interface boards/WXR board and the DPU boards takes place via a COMMON BUS. It provides parallel high speed data transfer, without disturbing the internal activities on the individual board. Access to the COMMON BUS takes place via bus couplers (master or slave) and bus requesters on each board and as per priority rules. A board which contains a bus master also has a bus requester, through which the board can claim access to the bus. A board which contains a bus slave (WXR board) can only respond to a data transfer operation claimed by another board with a bus master. Each board (I/O or DPU) can send an independent bus-request (BR*) signal to the bus arbiter (located on the DPU1 (PFD) board). The bus arbiter grants this request with a fairness protocol and sends a corresponding bus-grant (BG IN*) signal to the particular board. The board can now use the COMMON BUS (signal busy* is asserted). The power supply module, operating on 115v/400Hz aircraft supply voltage and controlled by the signal POWER DOWN, supplies all internal voltages in the unit.
 (2) Functional description The functional description of all the boards and the power supply module in the DMC is dealt with in this chapter.
 (a) DPU1 (PFD), DPU2 (ND), DPU3 (ECAM) boards
 (Ref. Fig. 007)

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 DPU Board - Block Diagram
 Figure 007

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1

 The general function of all three boards is identical. Each board
 can operate independently as it contains its own CPU and memory.
 The design of the board is based on the MC 68020 (CPU) concept,
 which enables the use of a powerful instruction set. Its RAM
 consists of the local RAM and the COMMON RAM (located on the DPU1
 (PFD) board).
 The access to the COMMON RAM, however, is via the COMMON BUS and
 hence the priority rules apply.
 Its whole ROM is located on the OBRM. This means that the
 complete software of each DPU is located on the OBRM.
 The main tasks of each DPU board are:

 -data processing, which includes scaling, filtering and execution of mathematical and logical functions
 -control of the DUs i.e. preparation of their input data, basic timing as well as start-, verify- and switching operations
 -execution of a part of the BITE (built-in test equipment) and fault isolation. The BITE memory is located on the DPU1 (PFD) board and can be accessed via the COMMON BUS.
 The DPU board can be sub-divided into the following main functional blocks:
 -Central Processing Unit (CPU)
 -local RAM and system EPROM
 -watch dog timer, address decoder and interrupt logic
 -bus requester and bus couplers
 -COMMON BUS time out control
 -MFPI
 -MFPII
 -DSDL control logic
 -COMMON RAM, BITE memory and bus arbiter Data communication between individual functional blocks (excepting COMMON RAM and BITE memory) on each board is carried out by the LOCAL-DATA-BUS (32 bit, bidirectional, three state), the LOCAL-ADDRESS-BUS (32 bit, uni-directional, three state) and the LOCAL-CONTROL-BUS (comprising various control signals). For the COMMON RAM and BITE memory, a separate MEMORY-BUS is provided. This bus consists of a MEMORY-DATA BUS.
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Central Processing Unit (CPU)
 The CPU is a 32-bit microprocessor from the MC68020 family. It
 is always in one of the following three processing states:

 -normal processing state, which is associated with instruction execution. In this state, the CPU fetches instructions/operands from its own system EPROM or from the COMMON RAM, processes them and stores the final result back in the COMMON RAM
　
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