1EFF : 106-149, 303-399, 1 31-63-00Page 50 1 1 Config-3 Aug 01/05 1 1 1CES 1

 Timing Diagram for Beam Processing
 Figure 017

 1EFF : 106-149, 303-399, 1 31-63-00Page 51 1 1 Config-3 Aug 01/05 1 1 1CES 1 6 Registers, WXR color code PROM and switching circuit

_ These three circuitries transfer the information from the main memory to the ND. The 4 BINs (12 bits) read of the four RAMs in the main memory are latched into a register in such a way, so that it can output three groups of 4 bits each ; where each group contains a bit from a BIN. The bits in each group are parallel-loaded into three shift registers, where a shift-right or shift-left takes place, depending on the signal UP/DOWN from the main memory read and refresh logic. Thus, at any given time, either the three outputs (i.e. a BIN) at QA or at QD of the shift register will address the WXR color code PROM. The WXR color code PROM contains eight color information for the BINs. It decodes the bits from the shift register and outputs three bits which determine the color of a grid point on the ND screen. This digital data (WXR COLOR) is transmitted via the driver and the switching circuit to the ND. In order to synchronize the start of this color-information-transmission with the start of the meander-scanning of the ND, a signal FRAME SYNC is coded in the color information to the ND. The switching circuit consists of relay units. During normal operation, the relay units transfer WXR information processed on this board to the ND. In case of a breakdown of this board or this DMC, the WXR information is processed in the back-up DMC3 and the switching circuit of the failed DMC transfers the output of the WXR board in the back-up DMC3 to the ND.
 1EFF : 106-149, 303-399, 1 31-63-00Page 52 1 1 Config-3 Aug 01/05 1 1 1CES 1

 7
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 8
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Delay counter, frame sync counter and line delay counter At the beginning of the WXR ON = HIGH phase i.e. just before the actual main memory read-operation, the delay counter generates a definite delay-period after which it enables the frame sync counter. During this delay-period, the DPU2 (ND) board informs the ND that it will be receiving color-information for BINs from the WXR board. The frame sync counter is basically responsible to activate a synchronizing signal, which can synchronize the start of color-information-transmission from this board with the start of meander-scanning of the ND. The main-memory, as already explained, is read using meander-scanning techniques. Thus, when the Y-address counter in the main memory read logic reaches the upper or lower limit of the writing mask, the X-address counter is enabled in order to increment its count by 1. In order to do this, the line delay counter provides the required signal.
Bus couplers, address decoder and word register There are three types of bus couplers on this board : data bus coupler, address bus coupler and control bus coupler. The data bus coupler is bidirectional and enables a data transfer between the LOCAL-DATA-BUS and the COMMON-DATA-BUS. Its direction is determined by the DPU2 (ND) board via the control bus coupler. The address bus coupler is uni-directional and transfers the addresses received through the COMMON-ADDRESS-BUS to the address decoder. The control bus coupler transfers control signals from the DPU2 (ND) board to the address decoder on the board. The address decoder consists of a line decoder and a PAL. Depending on whether a read- or write-operation is being executed through the COMMON-DATA-BUS, the line decoder transmits relevant control signals by decoding the address bits received via the address bus coupler. When complete valid data is received by this board via the COMMON-DATA-BUS, the PAL sends a data-acknowledge signal to the DPU2 (ND) board. It also sends enable-signals for the line decoder and the data bus coupler.
 1EFF : 106-149, 303-399, 1 31-63-00Page 53 1 1 Config-3 Aug 01/05 1 1 1CES 1

 There are a total of six word registers on this board:
 -two of which offer a buffer stage for information (status words) from this board to be transmitted to the DPU2 (ND) board through the COMMON-DATA-BUS
 -four of which offer a buffer stage for information (control words) transmitted by the DPU2 (ND) board through the COMMON-DATA-BUS to this board.
 The six word registers are cleared by power-on and are individually enabled by the address decoder.
 9 Test logic
_ This logic helps to test the WXR board. For this, the DPU2 (ND) board generates a test beam, which is fed to the WXR board. The test beam contains 1600 bits - 64 of which represent four control words and 1536 represent the BIN information. The WXR board processes the test beam like a normal WXR beam - it transmits the first 64 bits back to the DPU2 (ND) board and stores the BIN information in the main memory. The information read out of the main memory is compared to a set information transmitted by the DPU2 (ND) board and if these match, a test counter is incremented. The test counter output is monitored by the DPU2 (ND) board and if it reaches 256 in the prescribed period, the WXR board test is positive. During the test period, an exchange of control- and status-words takes place between the DPU2 (ND) board and the WXR board - the control words set definite signals to definite levels on the WXR board, where as the status words are checked by the DPU2 (ND) board for validity.
　
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