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The DSDL switching circuit is different on the three DPU boards. It consists basically of two relay units ; each unit having a double-pole two-way switching capability. During normal operation, the relay-units are not activated. A bidirectional data transfer between this DMC and the DU thus takes place. In the case of a breakdown of this DMC, one relay-unit is activated by the external signal DMC3 TRANSFER, and a bidirectional data transfer between the back-up DMC3 and the relevant DU takes place. In the case of a breakdown of an ECAM DU, the second relay-unit is activated by the external signal ND/ECAM TRANSFER and a bidirectional data transfer between an EFIS DU and the DPU3 (ECAM) board (via DPU2 (ND) board) takes place.
COMMON RAM, BITE memory and bus arbiter The COMMON RAM, the BITE memory and the bus arbiter are located on the DPU1 (PFD) board only. The COMMON RAM and the BITE memory are accessible to the DPU and I/O boards through the COMMON BUS. The COMMON RAM has a storage capacity for 16Kx16-bit words. It is divided into definite sections, where computed data from the DPU and I/O boards is stored intermediately until further use. It is addressed by the MEMORY-ADDRESS-BUS and data transfer takes place through the MEMORY-DATA-BUS. The memory address decoder provides the control-signals for the COMMON RAM. A special power supply line +5 V PROT. from the power supply module provides continuous power to the COMMON RAM even during a short-power-interrupt condition. The BITE memory has a total storage capacity of 2Kx16-bit words. A fault indication from any board during a self-test routine is stored in this memory for analysis during maintenance operations. It is accessed in the same manner as the COMMON RAM.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 22 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 The bus arbiter can receive four bus-request (BR*) signals simultaneously for the use of the COMMON BUS - three from the three I/O interface boards and one from the three DPU boards, which are daisy-chained. Based on the priority rules, the bus arbiter then grants request to that board with the highest priority-level. This is done by activating the specific bus-grant signal (BGIN*). The bus arbiter can transmit four bus grant signals - three to the three I/O interface boards and one to the three daisy-chained DPU boards. Once a bus-request is granted to a board, it asserts the signal BUSY* which informs the bus arbiter that the COMMON BUS is being used. The bus arbiter can treat 6 bus-requests (BR*) with priority and fairness protocol. Fairness: If 3 or more bus requests occur at the same time, all requests will be granted in priority sequence without interruption. The maximum waiting time of a requesting device is the duration of 5 common bus cycles incl. arbitration.
(b) I/O interface 1, 2 and 3 boards (Ref. Fig. 008) Each of the three interface boards consists y of three independent I/O (input/output) interfaces:
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the discrete I/O interfaces
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the ARINC I/O interfaces
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the serial interfaces. The complete management of these interfaces is carried out by the processor logic on each board. The main task of the processor logic is to handle all data passing through these interfaces, relabelling it when necessary and storing it in the COMMON RAM (on the DPU1 (PFD) board). It also fetches data from the COMMON RAM and guides it to external peripherals via these interfaces.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 23 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1
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