-------------------------------------------------------------------------------| CODES | COLORS | RED | GREEN | BLUE | | | | (%) | (%) | (%) | |-----------------------------------------------------------------------------| | 00 | Red gun control | 100 | 0 | 0 | | 01 | White/Black | 50 | 100 | 75 | | 02 | White/Cyan | 50 | 90 | 60 | | 03 | Magenta/Black | 80 | 5 | 80 | | 04 | White/Brown | 30 | 80 | 85 | | 05 | Green/Brown | 0 | 90 | 30 | | 06 | Cyan/Cyan | 10 | 70 | 85 | | 07 | Yellow/Black | 80 | 100 | 0 | | 08 | Cyan/Brown | 0 | 75 | 85 | | 09 | Amber/Black | 90 | 50 | 0 | | 0A | Yellow/Black 50% | 40 | 50 | 0 | | 0B | Red 50% | 50 | 0 | 0 | | 0C | Cyan | 0 | 65 | 85 | | 0D | White 100% NU | 100 | 100 | 100 | | 0E | Pattern | 1 | 1 | 1 | | 0F | Grey background | 18 | 33 | 24 | | 10 | Red gun cont prep. | 0 | 0 | 0 | | 11 | White 75% | 35 | 75 | 55 | | 12 | Brown | 20 | 15 | 0 | | 13 | White 50% | 20 | 50 | 35 | | 14 | Green/Cyan | 0 | 100 | 0 | | 15 | NU Red 100% | 100 | 0 | 0 | | 16 | NU Blue 100% | 0 | 0 | 100 | | 17 | NU Green 76% | 0 | 76 | 0 | | 18 | NU | 0 | 0 | 0 | | 19 | WXR synchro | 0 | 0 | 0 | | 1A | Blue | 0 | 65 | 85 | | 1B | Magenta | 65 | 0 | 85 | | 1C | Red | 75 | 0 | 0 | | 1D | Yellow WXR | 100 | 70 | 0 | | 1E | Green | 10 | 65 | 0 | | 1F | Blank | 0 | 0 | 0 |
 NOTE : NU codes for test purposes only.
____
 NOTE : The Weather Radar can use only the last 8 codes of the
____
 list.

R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 67

1201-299, 301-302,  1 Config-1 May 01/05
 1  1
 1CES  1

 7 Memory block
_ Memory of the SG is divided in 4 parts:
 a 6K 16 bit-words in EEPROM for the monitor program and the
_
 alphanumerics,

 b 10K 16 bit-words in EEPROM for the PFD, ENGINE, and part of
_
 the ND programs.

 c 15K 16 bit-words in RAM for current drawing program and
_
 data divided in:

 -
2 pages of 1K words each for rapidly refreshed data

 -
2 pages of 5K words each for slowly refreshed data

 -1 non paginated 3K for feedback data.
 d 1K 16 bit-word, located on a 1K word address field, for DUA
_ (DU anomaly). At any time, one page is used by the SG to build the current image while the other page receives via the serial link the necessary data for the next image. The EEPROMs will be programmed via the DSDL line. This shall take place only at the electrical power on setting (DMC + DU), and only if the program stored in the EEPROM does not match that which corresponds to the DMC software. There is no specific circuit on the SG to program the EEPROM "in situ". The RAMs are protected against short power interrupt (at least 3 seconds).
 NOTE : The alphanumerics field contains the description of
____ standard alphanumerics (available in 4 sizes) on one hand, and of special drawing characters on the other hand. The sizes are : 3, 3.5, 4 and 5 mm.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 68 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 8 Inputs/outputs controller

_ The I/O controller provides the timing for the SG system. It controls all the memory accesses and allows a shared memory access between the processor and the serial link interface.
 9 Serial link controller : SDL
_
 This function includes:

 -
a Transmitter/Receiver circuit performing the Serial/Parallel conversion, based on the Harris device HS 3282

 -
a LSI circuit whose function is to interface the serial link with the memory. It handles the direct memory access and generates the control signals according to the labels sent by the DMC

 -
a line driver circuit whose function is to interface the HS 3282 and the DSDL feedback line.

 10 Clock generator
__ The LSI circuit generates all the necessary clocks for the SG. The clock reference is a 16MHz oscillator, which must be matched with the WXR clock of the DMC.
 11 WXR link receiver
__ (Ref. Fig. 023)
 a WXR link decoder
_
 The functions of this circuit are:

 -
To receive the color bits and clock signals

 -
To extract the frame synchro signal

 -
To reset the FIFO memory and to enable the writing

 -
To trigger the LSI symbol generator.

 b FIFO memory
_ The size of the FIFO memory (64 x 3) is sufficient to take care of the slight frequency difference between the SG oscillator and the DMC WXR oscillator.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 69 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1

 WXR Link Receiver - Block Diagram
 Figure 023

R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 70 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1
　
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