1EFF : 106-149, 303-399, 1 31-63-00Page 33 1 1 Config-3 Aug 01/05 1 1 1CES 1 5 Bus logic

_ The following functional groups are discussed under this heading :
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bus request logic

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bus time out logic

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bus couplers.

 a Bus request logic
_ The bus request logic is integrated into a 20-pin gate array module. The gate array also contains the bus time out logic (discussed in this chapter) and the reset logic (discussed under processor logic). The bus request logic consists internally of a bus requester and a bus master control. When the CPU on any I/O interface board wants access to the COMMON BUS, it activates signal CE BUS* via the address decoder (in the processor logic). The bus requester recognizes this signal CE BUS* and sends the bus-request signal BR* to the bus arbiter (on DPU1 (PFD) board). When the request is granted by this bus arbiter, it asserts a bus-grant input-signal BG IN*. Access to the COMMON BUS by any one of the three I/O interface boards is based on priority rules i.e. I/O interface 1 board has the lowest priority among the three boards. Once the bus-grant has been accepted by a bus requester, it sends signal BUSY* to the bus arbiter to indicate that the bus is now being used by its CPU. Signals CE STATUS* (from the address decoder) and bit D15 (on CPU-DATA-BUS) are activated when the CPU claims access to the COMMON BUS. These two signals ensure that signal BUSY* is held in active state as long as communication with the COMMON RAM or BITE memory (both on DPU1 (PFD) board) continues. When the CPU no longer requires the COMMON BUS, it activates ADDRESS-STROBE signal AS* and signal BUSY* becomes inactive.
 1EFF : 106-149, 303-399, 1 31-63-00Page 34 1 1 Config-3 Aug 01/05 1 1 1CES 1

 b
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 c
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 The function of the bus master control in the gate array is to generate enable-signals for the bus couplers once access to the COMMON BUS has been attained, so that an information transfer between the local buses on the I/O interface board and the COMMON BUS can take place. The enable-signal EN ADDA* enables the local data and address bus couplers, whereas enable-signal ENS* enables the local control bus coupler. The bus master control is clocked by XCK68K from the clock generator and the bus-acknowledge signal BACK remains HIGH as long as the information transfer takes place. All output signals from the bus requester and the bus master control are reset when the reset logic, also in the gate array is initiated.
Bus time out logic The bus time out logic is also integrated into the 20-pin gate array module. It determines how long the CPU can claim access to the COMMON BUS. The time interval begins with signals CE BUS* and BACK going active i.e. when the CPU has attained access to the COMMON BUS, whereas the timing is monitored by clock XCK68K from the clock generator. On completion of the specified time interval, signal BERR* is activated in order to stop the CPU. This signal can also be activated when the reset logic, also in gate array, is initiated.
Bus couplers There are three types of bus couplers on each I/O interface board - the local data bus coupler, the local address bus coupler and the local control bus coupler and the local control bus coupler. The local data bus coupler consists of two bi-directional line drivers. They enable data transfer between the CPU-DATA-BUS (D00-D15) on each I/O interface board and the COMMON-DATA-BUS (BD00-BD15). They are enabled by the enable-signal EN ADDA*, which is generated by the bus master control when the I/O interface board has been granted access to the COMMON BUS. The direction of the line drivers is determined by signal R/W* from the CPU. The local address bus coupler consists of two uni-directional line drivers. When enabled by signal EN ADDA* (active LOW), they tranfer addresses, generated by the CPU from its CPU-ADDRESS-BUS (A00-A16) to the COMMON-ADDRESS-BUS (BA01-BA16).
 1EFF : 106-149, 303-399, 1 31-63-00Page 35 1 1 Config-3 Aug 01/05 1 1 1CES 1 The local control bus coupler enables a bi-directional transfer of control signals between the I/O interface board and the DPU1 (PFD) board (common RAM and BITE memory only) via the COMMON-CONTROL-BUS.

 (c) WXR board The echoes of 800 beams are received by the WRX antenna every half revolution (4 s.). Each beam echo contains 512 separate signals corresponding to the strength of the beam reflection at 512 separate points in the airspace in front of the aircraft. (Ref. Fig. 009) The strength of the reflection at each point is converted into a 3 bit code (1 BIN), which is the color mode for that particular point. This information is transmitted serially via an ARINC input channel to the WXR board, i.e. at any given time, 512 x 3 = 1536 serial bits or 512 BINs, which represent the color information of one beam, are received by the WXR board. In addition to the BIN information, the WXR board also receives four control words of 16 bits each as well as two signals, START SYNC and END SYNC, of approximately 3 bits each. The signal START SYNC heralds the start of the input word and signal END SYNC its end. The four control words are fetched by the DPU2 (ND) board and the BIN information is processed directly on this board. The WXR board can be sub-divided into the following main functional blocks: (Ref. Fig. 010)
　
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